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Memory control method with selective retention adn storate circuit

A storage circuit, a selective technology, applied in the direction of information storage, static memory, digital memory information, etc., can solve the problems that cannot be adapted

Active Publication Date: 2009-12-09
TELEFON AB LM ERICSSON (PUBL)
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Also, the size relationship between the retention SRAM portion and the non-retention SRAM portion is fixed during operation and may not be able to accommodate

Method used

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  • Memory control method with selective retention adn storate circuit
  • Memory control method with selective retention adn storate circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0020] Preferred embodiments will now be described in terms of SRAM circuits, such as embedded SRAMs for power critical applications.

[0021] figure 1 A schematic block diagram showing the structure of the SRAM according to the first preferred embodiment, which can be configured as an integrated memory circuit, and which consists of figure 1 The dotted box on the right-hand part indicates the memory section, and is divided into SRAM cells C 0，0 to C y，z groups 30-1 to 30-n. Each group is controlled by a dedicated control circuit comprising input terminals DR1 to DRn of data holding identifiers, logic units L1 to Ln, and gate or switch units S1 to Sn. In addition, the control circuit may also receive a global activity control signal A configured to set the memory circuit to a standby state or mode or to an active state or mode. The number of storage units in each of the groups 30-1 to 30-n can be selected as required, and the number determines the granularity of the retent...

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PUM

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Abstract

The present invention relates to a memory circuit and a method of controlling data retention in the memory circuit, wherein a supply signal is selectively switched to a respective one of at least two virtual supply lines (24) each shared by a respective one of a plurality of groups (30-1 to 30-n) of memory cells (C0,0 to Cy,z). The selective switching is controlled based on a global activity control signal (A), used for setting the memory circuit either into a standby state or into an active state, and a local data retention indication signal (DR1 to DRn) allocated to a dedicated group of memory cells. Thereby, the data retention part of the memory circuit can be adapted to the application and its state, and standby mode leakaged power is only dissipated in those memory cells for which data retentions actually required.

Description

technical field [0001] The present invention relates to a memory circuit having a plurality of memory cells for storing data, and to a method of controlling data retention in such a memory circuit. Background technique [0002] Random access memory typically includes an array of data storage locations, known as memory cells, where individual data elements, known as bits, can be held. Each memory cell can be addressed such that data from the external environment can be written to the memory cell, or data can be read from the memory cell and provided to the external environment. The time it takes to access data in any particular memory location is essentially independent of location, hence the name Random Access Memory. The word "static" in static random access memory (SRAM) refers to the memory's ability to hold data without having to constantly refresh or rewrite memory cells. This contrasts with "dynamic" random access memory (DRAM), which requires the memory cells to be ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C5/14
CPCG11C5/14G11C7/00G11C11/41
Inventor 科内利斯·H·范贝克莱
Owner TELEFON AB LM ERICSSON (PUBL)