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Delay circuit

A delay circuit and delay signal technology, applied in electrical components, pulse processing, power reduction through control/clock signals, etc., can solve the problems of delay circuit final delay time difference, deviation, etc.

Inactive Publication Date: 2008-12-10
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, there is a difference (or deviation from the expected value) in the final delay time of the delay circuit in the prior art

Method used

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Examples

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no. 1 example

[0021] Embodiments of the present invention will be explained below with reference to the drawings. FIG. 1 is a block diagram showing a delay circuit 100 according to a first embodiment of the present invention. As shown in FIG. 1 , the delay circuit 100 according to the present embodiment includes a reference pulse generation circuit 10 , a counter 20 , a delay signal output circuit 30 and a reset signal output circuit 40 .

[0022] The reference pulse generating circuit 10 has a feedback circuit 11 including a delay section for determining a time interval between reference pulses and generating a reference pulse train in response to an input signal. The feedback circuit 11 performs calculation by using a signal based on a delayed pulse train generated in a delay section in generating a reference pulse, a signal generated based on a delayed signal output from a delayed signal output circuit 30 (explained later), and an input signal. , and provide the result of the computatio...

no. 2 example

[0047] FIG. 3 is a block diagram showing a delay circuit 200 according to a second embodiment of the present invention. Incidentally, in FIG. 3 , the same symbols are assigned to the same components and structures as those in FIG. 1 , and their detailed explanations are omitted. In the first embodiment, the counter 20 is constituted by DFF circuits DFF1-DFF3. In contrast, in the delay circuit 200 of this embodiment, the counter 50 is constituted by a plurality of DFF circuits DFF1-DFFn (n is an integer greater than 1). Furthermore, the delay circuit 200 includes a selector 8 connected between a counter 50 corresponding to the counter 20 in the delay circuit 100 of the first embodiment and the delay signal output circuit 30 . Note that the structure and operation of the delay circuit 200 according to the present embodiment are the same as those of the delay circuit 100 according to the first embodiment except for the structure and operation of the counter 50 and the newly adde...

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PUM

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Abstract

A delay circuit to generate and output a delayed signal delayed from an input signal includes a reference pulse generating circuit to generate a reference pulse train in response to the input of the input signal, the reference pulse generating circuit having a feedback circuit containing a delay portion to determine a time interval between the reference pulses, a counter to output count signals based on a reference clock, the counter receiving the reference pulse train generated by the reference pulse generating circuit as the reference clock, and a delayed signal output circuit to generate and output the delayed signal based on the input signal and the count signals.

Description

technical field [0001] The present invention relates to a delay circuit, in particular to a delay circuit preventing current from flowing through a drive circuit. Background technique [0002] A drive circuit for driving a load such as a motor is generally equipped with a delay circuit to prevent current from flowing through the drive circuit. FIG. 4 shows a driving circuit 400 in the prior art. The drive circuit 400 includes a shoot-through current prevention circuit 401 composed of delay circuits 402a and 402b and inverters INV1 and INV2, and CMOS transistors (PMOS transistor P1 and NMOS transistor N1). The CMOS transistor is connected to the shoot-through current prevention circuit 401, and is connected between the power supply potential and the ground potential. In addition, a load (not shown) such as a motor is connected to the output OUT of the CMOS transistor. [0003] The delay circuit 402a outputs a delayed signal whose rising edge is delayed from the rising edge...

Claims

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Application Information

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IPC IPC(8): H03K5/135
CPCH03K5/04H03K5/1515H03K19/0016
Inventor 元结敏彰
Owner RENESAS ELECTRONICS CORP