A half-bridge module and packaging method

Abstract

The invention discloses a half-bridge module and a package method. The half-bridge module is arranged in a way that two chips are used as sub-units arranged in a parallel and in a group way. The half-bridge module comprises an upper half-bridge module and a lower half-bridge module, wherein the upper half-bridge module comprises a plurality of two-chip direct-parallel upper half-bridge sub-units, an auxiliary source driving signal terminal, a grid driving signal terminal, a drain power terminal and a source power terminal, the lower half-bridge module comprises a plurality of two-chip direct-parallel lower half-bridge sub-units, an auxiliary source driving signal terminal, a grid driving signal terminal, a drain power signal terminal and a source power signal terminal, the drain power terminal of the lower half bridge is electrically connected with the source power terminal of the upper half bridge, and structures of the power signal terminal and the driving signal terminal are of binary tree-shaped structures. With the adoption of the half-bridge module or the package method, the distribution difference of stray inductance of a circuit can be reduced, and the relatively good current sharing characteristic of a silicon carbide chip is achieved.

Description

technical field [0001] The invention relates to the technical field of module packaging, in particular to a half-bridge module and a packaging method. Background technique [0002] As the third-generation high-temperature wide-bandgap semiconductor device with the most mature technology, relatively stable structure and the best industrialization, silicon carbide devices have high blocking voltage capability, high switching frequency, lower on-state resistance, and lower switching losses and higher thermal conductivity. In recent years, although its material performance and manufacturing process have been greatly improved, compared with similar silicon-based devices, its chip size is smaller and its current rating is lower. For high-current applications, the current chip size and even the chip size that may be technically achieved in the future are not enough to realize the high-current breaking capability of a single chip. This is because an excessive chip size leads to a ...

AI Technical Summary

Problems solved by technology

The current welding module adopts multi-chip parallel connection to achieve a higher current level, but with the increase in the number of parallel chips, it is difficult to achieve a symmetrical layout, which makes the distribution of stray inductance uneven

Images