Frequency-adjusting device

A technology of frequency adjustment and frequency division, applied in the direction of generating/distributing signals, etc., can solve problems such as clock signal glitches, clock signal duty cycle mutations, microprocessor operation errors, etc.

Active Publication Date: 2009-06-03
RDA MICROELECTRONICS SHANGHAICO LTD
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

In this way, the switching between the new frequency and the old frequency makes the duty cycle of the clock signal output by the frequency divider change suddenl

Method used

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Example Embodiment

[0054] Example

[0055] Figure 7 It is a schematic diagram of the composition structure of the frequency adjustment device according to the embodiment of the present invention. Such as Figure 7 As shown, in this embodiment, the frequency adjustment device includes a microprocessor, a first register, a D flip-flop, a comparator, a second register, a third register, a counter, a frequency divider, an enable signal generation module, and an AND gate. ; Among them, the D flip-flop will read the first frequency division coefficient from the first register, and delay the first frequency division signal containing the first frequency division coefficient by one main clock cycle to obtain the second frequency division coefficient containing the second frequency Frequency division signal. The third register stores the preset first threshold and second threshold, and the first threshold is preset to 16 and the second threshold is 32. The frequency division coefficient before resetting se...

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Abstract

The invention relates to a frequency-adjusting device which comprises a microprocessor, a first register and a frequency-adjusting circuit. The microprocessor sets up a frequency division coefficient according to self workload or a working state; the first register stores the frequency division coefficient set up by the microprocessor; and the frequency adjusting circuit uses the read frequency division coefficient as a first frequency division coefficient; the first frequency division coefficient is compared with a delayed second frequency division coefficient and counted according to an effective comparison signal and a clock signal of the second frequency division coefficient; if the counting value equals to a first threshold value, a working clock signal is a low level signal; and when the counting value is smaller than the first threshold value or equals to a second threshold value, the working clock signal is a clock signal corresponding to the second frequency division coefficient. When the frequency division coefficients change, a duty cycle of the working clock signal of the device shows no mutation, thereby causing smooth transition to be achieved between working clock signals before and after the change of the frequency division coefficients. The device can be widely applied to electronic information systems.

Description

technical field [0001] The invention relates to a frequency switching technology, in particular to a frequency adjustment device. Background technique [0002] In practical applications, many circuit chips can adjust their operating frequency according to the workload or working state to reduce energy loss. For example, for a baseband chip of a GPS (Global Position System) receiver, when its working channel (channel) increases, the baseband chip adjusts its operating frequency up; when its working channel decreases, the baseband chip adjusts its operating frequency down. [0003] figure 1 It is a schematic diagram of the composition and structure of the frequency adjustment device of the circuit chip in the prior art. Such as figure 1 As shown, the frequency adjustment device of the circuit chip is composed of a microprocessor, a register and a frequency divider; wherein, the microprocessor adjusts the frequency division coefficient, and stores the adjusted frequency divi...

Claims

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Application Information

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IPC IPC(8): G06F1/08
Inventor 王伟蒋松鹰陆建华
Owner RDA MICROELECTRONICS SHANGHAICO LTD
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