4results about How to "Avoid running errors" patented technology

The invention discloses an atomic operation processing unit, an exception processing method, a display card and equipment, and belongs to the field of chips. The atomic operation processing unit comprises an anomaly detection circuit, an atomic operation processing circuit and an anomaly processing circuit. The anomaly detection circuit is connected with the atomic operation processing circuit; the atomic operation processing circuit is connected with the exception processing circuit; the anomaly detection circuit is used for outputting the input data and anomaly information to the atomic operation processing circuit under the condition that the input data is abnormal; the atomic operation processing circuit is used for executing atomic operation based on the input data to obtain an atomic operation result; the atomic operation result and the exception information are output to the exception processing circuit; and the exception handling circuit is used for selectively discarding the atomic operation result or writing the atomic operation result into the storage unit based on the exception information. The atomic operation processing unit supports anomaly detection and anomaly processing in the atomic operation execution process, and the reliability of atomic operation execution can be guaranteed.

The present application relates to the field of industrial automation control, and specifically provides a programmable logic controller program automatic acquisition method, a storage medium and an electronic device, aiming at solving the problem that multiple types of processor programs cannot be automatically collected. To this end, the acquisition method of the present application comprises: acquiring the type of central processing unit contained in the programmable logic controller; the type includes a standard central processing unit and a fail-safe central processing unit; according to the type, determining the program upload mode of the programmable logic controller; according to the program upload mode, uploading the program of the programmable logic controller. The present application can realize compatible collection of standard central processing unit and fail-safe central processing unit device programs, and reduce the labor cost and time cost of industrial device program operation and maintenance.

The invention discloses a dynamic configuration mapping system and method for VR head-mounted display equipment. In the invention, through the design of each sub-module of the intelligent mapping matching module, the development and maintenance cost is greatly reduced. The configuration validity verification sub-module checks the integrity of a configuration structure in advance, and running errors caused by invalid configuration are avoided; the device name matching sub-module adopts inclusion relation search instead of accurate matching, supports a device group and wildcard character form, and does not need to compile a large number of if-else codes like a traditional scheme; the mapping index positioning sub-module corresponds to equipment and configuration one by one through array indexes, new equipment only needs to add corresponding items in a configuration file, core codes do not need to be modified, the access period of the new equipment is remarkably shortened, meanwhile, the workload of regression testing is reduced, the risk of configuration conflicts is avoided, and the efficiency is improved. When the fault-tolerant degradation processing sub-module does not find the matching configuration, the wildcard character is automatically triggered to carry out the default configuration or load the default configuration, so that the interface component is ensured to be normally rendered all the time, and the robustness of the system and the user experience are improved.

The invention provides a DDR4 function test system and method, and the system comprises an FPGA module which is connected with a to-be-tested DDR4, and is used for obtaining a test information instruction, transmitting an input test signal to the to-be-tested DDR4 based on the test information instruction, and obtaining an output test signal from the to-be-tested DDR4, dDR4 storage data information is obtained based on the input test signal and the output test signal; the configuration circuit module is connected with the FPGA module and is used for supporting the normal operation of the FPGA module; according to the invention, the FPGA module can obtain DDR4 storage data information so as to evaluate the storage data performance of the DDR4.