Fast powering-up of data communication system

Abstract

A data communication system has a transmitter with a first clock-generation circuit, and a receiver with a second clock generation circuit. At least a specific one of the clock-generation circuits is powered-down between consecutive data bursts. The system expedites the starting up of operational use of the system upon a power-down of the specific clock-generation circuit. The system presets at a predetermined value an operational quantity of the specific clock-generation circuit at the starting up.

Description

technical field [0001] The present invention relates to a data communication system comprising a transmitter with a first clock generating circuit and a receiver with a second clock generating circuit. Background technique [0002] High-speed data communication links typically utilize input-output (IO) signaling techniques that require a fairly "static" portion of power consumption during operation, independent of the actual data rate. In most cases, a significant portion of this power consumption is related to the need to drive line terminations to obtain reliable signal behavior on the transmission line. One commonly used driver structure is a resistively loaded differential pair. Other line driver solutions that provide termination resistors at one or both ends are also possible. An example of the latter is a full-bridge driver structure with source-series termination and far-end line termination. For example, in "Embedded Low-Cost 1.2Gb / s Inter-IC Serial Data Link in ...

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Problems solved by technology

Although this results in an easily understood inefficient system

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