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Display panel with optimized bonding pad distribution of gate driver

A gate driver and display panel technology, applied to instruments, static indicators, etc., can solve the problems of restricted gate driver pad layout, restricted gate driver 15 size, etc.

Inactive Publication Date: 2012-07-25
AU OPTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, in the pad layout 20, the upper and lower edge pads of the gate driver 15 are arranged as evenly as possible, that is, the output pad 22 and the input pad 243 are designed to have an area ratio close to 1:1. , such a design also limits the size of the gate driver 15
[0005] To sum up, the pad layout of the gate driver is a major factor determining the size of the gate driver. Due to the development of integrated circuit technology, it is not difficult to manufacture a small-sized gate driver, and reducing the size means reducing the size of the gate driver. cost, however, the size of the gate driver is limited by the pad layout of the gate driver

Method used

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  • Display panel with optimized bonding pad distribution of gate driver
  • Display panel with optimized bonding pad distribution of gate driver
  • Display panel with optimized bonding pad distribution of gate driver

Examples

Experimental program
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Embodiment Construction

[0032] Please refer to image 3 , image 3 It is a schematic diagram of the liquid crystal display panel of the present invention. The liquid crystal display panel 30 includes a plurality of source drivers 31 , a plurality of gate drivers 32 and a display area 33 . The display area 33 includes a plurality of data lines 34 and a plurality of scan lines 35 . The source driver 31 is disposed on the first junction area 36 and is electrically connected to the plurality of data lines 34 . The gate driver 32 is disposed on the second junction area 37 and is electrically connected to the plurality of scan lines 35 .

[0033] Please refer to Figure 4 , Figure 4 It is a schematic diagram of the first embodiment of the pad layout of the gate driver of the present invention. exist image 3 In the second bonding area 37 , the pad layout 40 of each gate driver 32 includes a plurality of output pads 421 , 422 and a plurality of input pads 441 , 442 . The input pads 441 and 442 inclu...

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PUM

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Abstract

The invention discloses a display panel with optimized bonding pad distribution of a gate driver, which comprises a display area, a first bonding area and a second bonding area. The second bonding area is used to be bonded with the gate driver. The second bonding area comprises a plurality of input bonding pads and a plurality of output bonding pads. The input bonding pads are arranged in the regions on both sides of the second bonding area along a first direction, and only the input bonding pads are arranged along a second direction. The output bonding pads are arranged in the intermediate region of the second bonding area along the first direction and only the output bonding pads are arranged along the second direction.

Description

technical field [0001] The invention relates to a display panel, in particular to a display panel which optimizes the pad layout of a gate driver. Background technique [0002] Please refer to figure 1 , figure 1 A schematic diagram of a prior art liquid crystal display. The liquid crystal display 10 includes a display panel 11 , a printed circuit board 12 , a plurality of flexible circuit boards 13 , a plurality of source drivers 14 and a plurality of gate drivers 15 . Generally, the combination of the display panel 11 and the printed circuit board 12 uses a tape-and-reel chip bonding (Tape Automated Bonding, TAB) or chip glass bonding (Chip On Glass, COG) technology. Compared with the tape-and-reel chip bonding technology, the chip glass bonding technology uses fewer flexible circuit boards 13 and printed circuit boards 12 . In order to further reduce the number of flexible circuit boards 13 and the number of layers of printed circuit boards 12, products using chip gla...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G09G3/20G09G3/36
Inventor 黄文江许胜凯
Owner AU OPTRONICS CORP