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Barrier synchronization apparatus, barrier synchronization process system and method

A technology for synchronizing equipment and synchronizing algorithms, which can be used in program control design, instrumentation, electrical digital data processing, etc., and can solve problems such as limited network structure

Active Publication Date: 2013-04-10
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, depending on the configuration of hardware to be employed for high-speed calculations, when multiple nodes are connected to each other via a network, the network configuration between nodes may be limited

Method used

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  • Barrier synchronization apparatus, barrier synchronization process system and method
  • Barrier synchronization apparatus, barrier synchronization process system and method
  • Barrier synchronization apparatus, barrier synchronization process system and method

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no. 4 example

[0175] The fourth embodiment basically includes the same configuration as the second embodiment. More specifically, in the fourth embodiment, figure 2 The node 1 shown is arranged in figure 1 in the computer network shown, and Figure 9 The reduction operator 8 shown is arranged in the node 1 .

[0176] On the other hand, in the fourth embodiment, instead of Figure 10 The reduction operation device 8 shown, the reduction operation device 8A is arranged as Figure 18 shown. The reduction operation device 8A basically includes the same configuration as the reduction operation device 8 . However, in the reduction operation device 8A, the type register of the control register 822 is omitted.

[0177] For this reason, in the fourth embodiment, the packet includes information indicating the type of arithmetic operation. Since the arithmetic operation type can be known in advance, before the reduction operation, the arithmetic operation type is input to the setting processor...

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Abstract

A barrier synchronization apparatus includes a receiving device which transmits a first synchronization signal to a synchronization device when the first synchronization signal in which a transmission destination is set in advance according to setting conditions including an algorithm of the barrier synchronization and an execution condition is received. A synchronization device synchronizes n first synchronization signals which are set in advance according to the setting conditions, wherein n is a positive integer, and designates transmission of m second synchronization signals in which transmission destinations are set in advance according to the setting conditions after the synchronization is established, wherein m is a positive integer. A transmitting device transmits the second synchronization signals to m transmission destinations set in advance, when a transmission designation information indicating the transmission designation is received from the synchronization device.

Description

[0001] Cross References to Related Applications [0002] This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2008-295115 filed on November 19, 2008, the entire contents of which are hereby incorporated by reference. technical field [0003] Embodiments of the present invention discussed herein relate to a barrier synchronization device, a barrier synchronization system, and a barrier synchronization method. Background technique [0004] Barrier synchronization is known as a method of synchronizing multiple processes executing in parallel with each other. In barrier synchronization, set barrier points. A barrier point is a point at which synchronization occurs. A process performing barrier synchronization temporarily suspends execution when it reaches a barrier point. When all processes performing barrier synchronization and executing in parallel reach the barrier point, the process performing barrier synchronization...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/173
CPCG06F9/522G06F9/4843G06F1/12G06F9/30087G06F9/3851
Inventor 平本新哉安岛雄一郎井上智宏
Owner FUJITSU LTD