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Device and method for enabling multi-core environment provided on bus

A bus, enabling technology, applied in the field of microelectronics, which can solve problems such as timing offset and high frequency noise

Active Publication Date: 2010-09-01
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, driving the I / O signal to the actual pull-up termination impedance will cause high frequency noise (High Frequency Noise), reflection (Reflection), ringing (Ringing), timing offset (Timing Displacement) and other defects

Method used

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  • Device and method for enabling multi-core environment provided on bus
  • Device and method for enabling multi-core environment provided on bus
  • Device and method for enabling multi-core environment provided on bus

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Embodiment Construction

[0022] In order to make the features and advantages of the present invention more comprehensible, preferred embodiments are specifically cited below, together with the attached drawings Figure 1 to Figure 8 , to explain in detail. The description of the present invention provides different examples to illustrate the technical features of different implementations of the present invention. Wherein, the configuration of each element in the embodiment is for illustration, not for limiting the present invention. Moreover, part of the symbols in the figures in the embodiments is repeated, for the sake of simplicity of description, it does not imply the relationship between different embodiments.

[0023] In view of the bus interface discussed in the prior art and related technologies used to transfer data between devices in integrated circuits, in the following, Figure 1 to Figure 3 will illustrate the problems created by multiple actively terminated buses, while Figure 5 to ...

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Abstract

A device and method for enabling a multi-core environment provided on a bus is provided, wherein the bus is subjected to the Impedance control by an active terminal. The method includes: generating an indicating signal by a location array arranged in a processor core, the indicating signal indicates one of nodes in the bus or at the terminal of the bus. One node is controlled by a location-based multi-core logic circuit configured in a driver be driven. The controlling method includes: if the indicating signal designates one node to the terminal of the bus, enabling a pull-up logic circuit and a first pull-down logic circuit, if the indicating signal designates one node into the bus, enabling a pull-up logic circuit and a second pull-down logic circuit. The invention can provide good bus active impedance control for a plurality of multi-core processors, meanwhile, reserve the required transmission line characteristic.

Description

technical field [0001] The present invention relates to microelectronics, and in particular to a mechanism for enabling and maintaining multiple processor contexts on a bus that require active control of bus termination impedance, wherein the multiple processor contexts include A processor package substrate (Processor Package Substrate) has a plurality of processor dies on it. Background technique [0002] Currently, in order to support fast incident wave switching (Incident Wave Switching) with low output amplitude (Low Output Swing), the bus architecture provides a point-to-point bus interface (Point- To-Point Bus Interface). In addition to providing a point-to-point bus interface, the bus architecture also requires the microprocessor (or other devices) to provide an internal termination impedance control circuit to dynamically adjust the termination impedance on the point-to-point bus, where the impedance value can generally be selected to match the characteristics of th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/40
CPCG06F13/40G06F13/4072
Inventor 达鲁斯·D·嘉斯金斯詹姆斯·R·隆柏格
Owner VIA TECH INC
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