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Method and apparatus for diagnosing an integrated circuit

An integrated circuit, input signal technology, applied in the field of integrated circuit failure analysis

Active Publication Date: 2013-06-12
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, while the scan chain diagnostic method determines when an IC has failed, it creates special problems when the fault occurs within the delay / buffer chain between flip-flops

Method used

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  • Method and apparatus for diagnosing an integrated circuit
  • Method and apparatus for diagnosing an integrated circuit
  • Method and apparatus for diagnosing an integrated circuit

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Embodiment Construction

[0018] The making and using of the presently shown embodiments are described in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments described merely indicate specific ways to make and use the invention, and do not limit the scope of the invention.

[0019] now refer to figure 1 , a schematic diagram representing a system 100 for diagnosing an integrated circuit (IC) is shown. The system 100 includes a buffer 111 and a diagnostic unit 120 . Buffer 111 includes a buffer-type logic operator typically placed between flip-flops in the circuit to drive the signal to the next element in the circuit. Buffer 111 can also delay signals, among other things, to keep elements in the circuit synchronized. Buffer 111 receives buffer chain signal 101 and sends buffer chain signal 101 to the next element in the system.

[0020] Diagnosti...

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Abstract

System and method for diagnosing failures within an integrated circuit is provided. In an embodiment, the apparatus includes a diagnostic cell coupled in series with a buffer chain. The diagnostic cell includes a plurality of logic operators that when activated invert a signal received from the buffer chain. The inversion of the signal from the buffer chain allows the diagnostic cell to determinethe location of a failure within an integrated circuit previously determined by a scan chain design for test methodology to contain a failure.

Description

[0001] This application claims priority to US Provisional Application Serial No. 61 / 163,543, filed March 26, 2009, entitled "Method and Apparatus for Diagnosing an Integrated Circuit," which application is hereby incorporated by reference. technical field [0002] The present invention relates generally to a system and method for integrated circuit fault analysis, and more particularly to a system and method for locating faults in integrated circuits that have been identified through scan chain testing. Background technique [0003] Modern circuit design incorporates methods and hardware capable of testing integrated circuits (ICs) at the point of production completion. Circuit designers call this Design for Test (DFT) or Design for Testability. When the IC product is complete, the IC tester utilizes the methods and hardware involved in the DFT design process to apply fabrication tests. In this way, the IC tester verifies that the IC hardware does not contain defects that c...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/28
Inventor 唐健霖张简维平刘钦洲
Owner TAIWAN SEMICON MFG CO LTD