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Parallel scrambling and descrambling processing device and method

A processing device and descrambling technology, which is applied in the field of communication, can solve the problem of large fans of low-bit registers, and achieve the effect of reducing the fan-out coefficient

Active Publication Date: 2014-06-04
SANECHIPS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0040] The present invention is made in consideration of the problem of excessive fan-out of low registers in the prior art. Therefore, the main purpose of the present invention is to provide a parallel scrambling / descrambling processing device and method to solve the problems in the prior art. above question

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  • Parallel scrambling and descrambling processing device and method
  • Parallel scrambling and descrambling processing device and method

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Embodiment Construction

[0064] The invention divides the parallel scrambling code sequence generating circuits into several groups, and the circuit structure of each group is completely the same, so the reuse efficiency of the circuits can be improved, and the design time can be greatly saved. Each group of circuits contains m registers and corresponding calculation logic. The calculation logic of each group of circuits is exactly the same, and the m registers in this group are used to calculate the value of each register in the next shot. All the scrambling code sequences can be generated simply by assigning different initial values ​​to the registers of each group of circuits.

[0065] In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0066] Device embodiment

[0067] According to an embodiment of the present inven...

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Abstract

The invention discloses a parallel scrambling and descrambling processing device and a parallel scrambling and descrambling processing method. The device comprises a generating module and a processing module, wherein the generating module is used for calculating to generate a k-bit parallel scrambling sequence according to a formula of Dn+k=Ak*Dn; and the processing module is used for performing scrambling and descrambling processing on the input data according to the k-bit parallel scrambling sequence generated by the generating module. Therefore, a fan-out coefficient of a low register can be reduced.

Description

technical field [0001] The present invention relates to the communication field, in particular to a parallel scrambling / descrambling processing device and method. Background technique [0002] In the communication system, the signal is transmitted bit-serially during the transmission process, but the clock signal of the sending node is not transmitted, and the data receiving clock required by the receiving end is extracted from the received data signal. According to the commonly used clock data recovery (CDR) principle, clock recovery is completed by the continuous change of the data signal (0 and 1). If there are long strings of 0s or long strings of 1s in the received data stream, it cannot be accurately recovered. Receive clock, inaccurate receive clock will result in data loss or reception error. In order to accurately recover the receiving clock at the receiving end, it is necessary to prevent long strings of 0s or long strings of 1s from appearing in the transmitted d...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L29/06H04L7/00
Inventor 丘正前
Owner SANECHIPS TECH CO LTD
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