Laterally diffused metal oxide semiconductor (LDMOS) and manufacturing method thereof

Abstract

The invention discloses an LDMOS. Two PN junctions isolated are arranged between a drain end (181) and a substrate (10). The P area of the first PN junction is a p-shaped substrate (10), and the N area is an n-shaped buried layer (11). The P area of the second PN junction is a p-shaped epitaxial layer (20), and the N area is an n-pit (171) and an n-shaped heavily doped area (181). The isolating ring consisting of an n-shaped heavily doped area (184), an n pit (173) and an n pit (12) is arranged on the four sides of the LDMOS device. The bottom of the whole isolating ring is contacted with the n-shaped buried layer (11). The invention also discloses a method for manufacturing the LDMOS. The LDMOS and the method can effectively solve the problem that the drain end (181) and the substrate (10) may be connected electrically.

Description

technical field [0001] The invention relates to an LDMOS (laterally diffused MOS, laterally diffused MOS transistor) device. Background technique [0002] see figure 1 , which is a schematic cross-sectional view of an existing LDMOS. There is an n-type buried layer 11 on the p-type substrate 10 , and there is an n-well 12 further above. The depth of the n-well 12 is usually greater than 2 μm, and is also called a deep n-well. There are multiple isolation regions 13 in the n well 12, and these isolation regions 13 isolate the n well 171 and the p well 172 in the n well 12 from each other. There is an n-type heavily doped region 181 in the n well 171, which serves as the drain of the LDMOS device. The p-well 172 has an n-type heavily doped region 182 and a p-type heavily doped region 183, which are connected to serve as the source of the LDMOS device. There is a gate oxide layer 14 on the n-well 12, and a gate 15 on the top, serving as the gate of the LDMOS device. There...

AI Technical Summary

Problems solved by technology

Under inductive loads and some special applications, the potential of the drain terminal 181 may be lower than zero potential, while the substrate 10 is always at zero potential. At this time, the PN junction between the drain terminal 181 and the substrate 10 will be forward conducting , which causes leakage current in the LDMOS device

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