A verification method of SOC hardware and software co-simulation based on network communication protocol

Abstract

An SOC (System on a Chip) software and hardware collaborative simulation verification method based on network communication protocol is provided, which comprises the steps of: firstly, constructing a test platform end and a test excited end; and then carrying out data exchange through a self-explanatory data packet format, wherein the test platform end is a network server, including verilog design, System C model and a server packing / unpacking module written in C++ under the operation of a third-party simulator; the test excited end is a network client, including a test software and a client packing / unpacking module. The self-explanatory data packet format includes a reading / writing format on a bus, a reading / writing format of a VPI (Virtual Path Identifier) and simulative behavior control. In the invention, the compiling of the test excitation is simplified and the compiling time is saved, and the simulation velocity is increased and the test completeness of verilog design is improved.

Description

technical field [0001] The present invention relates to platform construction and test incentive software development for SOC software-hardware co-simulation verification, in particular to a SOC software-hardware co-simulation verification method based on network communication protocol, specifically applicable to self-explanatory data packet format in SOC software-hardware co-simulation Applied in the authentication method. Background technique [0002] SOC verification includes verification of hardware circuit design and verification of software, and the combination of the two is called software-hardware co-simulation. At present, the main verification schemes are: verilog direct excitation, model simulation or FPGA: [0003] Verilog direct stimulus: use verilog language in the test platform to translate the software test stimulus into the timing of the input port of the hardware design, directly drive the verilog design, and collect comparison data at the output port of th...

AI Technical Summary

Problems solved by technology

[0007] The purpose of the present invention is to overcome the flaws and problems of single test-stimulus writing language, longer compilation time, lower simulation speed, and imperfect verilog design and verification existing in the prior art, and provide a test-stimulus writing language freedom, SOC software-hardware co-simulation verification method based on network communication protocol with short compilation time, high simulation speed, and perfect verilog design verification

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