4results about How to "Save compilation time" patented technology

The present disclosure provides a data processing method and device, electronic equipment and computer readable storage medium, the method comprising: obtaining configuration information to be processed, wherein the configuration information is information for indicating target data to be deleted; generating a target deletion execution instruction according to the configuration information; sending the target deletion execution instruction to a database storing the target data based on a preset data operation interface, the database being configured to precompile the target deletion execution instruction, wherein the preset data operation interface supports placeholders and precompilation of the target deletion execution instruction; and deleting the target data in the database according to the target deletion execution instruction. According to the embodiments of the present disclosure, the target data in the database can be conveniently and efficiently deleted.

The present application belongs to the technical field of knowledge compilation and network reliability analysis, and particularly relates to a network reliability intelligent computing method and system for a logical decision graph, comprising: modeling a network system as a triple data structure composed of a network topology graph, a terminal node set and an edge availability probability set; determining a topology order of network nodes and network edges based on the triple data structure; constructing a full binary tree vtree with leaf nodes corresponding to network edges one by one according to the topology order; and compiling the network topology graph into a zero-suppression statement logical decision graph using the vtree, wherein the zero-suppression statement logical decision graph is used to represent a set of valid subgraphs that satisfy terminal node connectivity; and recursively calculating a reliability value of the network system based on the zero-suppression statement logical decision graph.

This invention discloses a SoC chip simulation verification method and system based on static and dynamic package separation. The method includes: acquiring simulation resources of the SoC chip to be verified; dividing the simulation resources into static and dynamic parts; the static part includes at least chip design code and basic verification environment components that do not need to be modified in the current verification stage, and the dynamic part includes at least verification test cases that need to be modified; encapsulating the static part into a static package and the dynamic part into a dynamic package; compiling the static package to execute the initialization simulation process, and saving the current initialization simulation state after the initialization simulation process is completed; compiling the dynamic package; loading the saved initialization simulation state, and executing the verification test cases in the dynamic package based on the restored initialization simulation state. This method avoids repeated compilation of large static resources due to modification of test cases, significantly shortens compilation time, and improves the verification efficiency and iteration speed of large-scale SoC chips.

The invention relates to a multi-server parallel compiling method and system based on large model aided decision making and a medium, and relates to the technical field of software compilation, the method comprises the following steps: obtaining a source code of a to-be-compiled project, and splitting the project into a plurality of independent compiling modules; based on the historical compilation data and the current server resource state, generating a configuration file containing a module allocation strategy through a large model; according to the configuration file, a compiling task is distributed to a plurality of servers through Jenkins Pipeline to be compiled in parallel; and collecting performance data in a compiling process, and feeding back the performance data to the large model to optimize a subsequent compiling strategy. Through large model intelligent analysis and a multi-server parallel compiling technology, the compiling time can be remarkably shortened, the resource utilization rate is improved, and dynamic optimization and self-adaptive adjustment of a compiling strategy are achieved.