17results about How to "Save compilation time" patented technology

The invention relates to the field of network page updating, and discloses an efficient front-end code real-time updating method and device and a storage medium, and the method comprises the following steps: initializing a front-end item; a partition recognition method is adopted for front-end items, and the dependency relationship between the items is divided into a plurality of sub-graphs; performing code operation identification on the front-end items by adopting a code analysis tool, and performing operation classification; selecting corresponding updating mechanisms according to different operation classifications; in combination with an incremental compiling method of Webpack and Vite, code incremental compiling is realized through module dependency graph optimization and enhanced analysis; carrying out real-time hot updating on the codes by adopting a multi-level differential hot updating method; and a cache control mechanism is introduced, so that front-end resources are updated in time when codes are subjected to real-time hot update. According to the method and the device, the front-end page updating efficiency and accuracy are improved.

The invention discloses a parallel compiler compiling method and system supporting multiple operating systems, which can fully utilize the advantages of a multi-processor or multi-core system and process a plurality of compiling tasks at the same time by acquiring a parallel compiling file, thereby greatly shortening the compiling time. The parallel compiling can significantly improve the compiling speed of large files, especially for complex software projects, the development cycle can be accelerated, and the development efficiency can be improved. A main function node is transformed, AST tree nodes corresponding to operating system interfaces are generated in combination with parallel compiling parameters, and then the AST tree nodes are inserted into an AST tree for node transformation operation, so that compiled files can run on a plurality of operating systems. According to the method, the barrier between different operating systems is broken, a developer does not need to independently write and maintain codes of different versions for each operating system, and the development and maintenance cost is reduced. The method allows adjustment according to different parallel compilation parameters to adapt to various compilation requirements.

The invention discloses a method for improving SPA application development performance. The method comprises the steps that an npm package installer is adopted to initialize an SPA application so as to manage application dependency in a unified mode; splitting dependent packages and codes with high computing power in the SPA application so as to reduce the number of files when an npm package manager compiles and packages; performing a Wasm conversion test and conversion on the high-computing-power code, and performing Wasm compilation on the dependent package to improve the compilation speed; judging updating of the dependent package in the application installation directory by adopting a package detector so as to re-execute the compiling work of the dependent package; and integrating the front-end framework with the Wasm through SPA application configuration so as to realize shunt loading of the framework structure. According to the method, front-end dependence rapid compiling and loading can be achieved, the construction performance and the construction speed are improved as much as possible, the pressure of an npm package manager is relieved, meanwhile, the compiling speed is improved, and the limitation of traditional SPA application compiling and packaging is solved.

The invention relates to the technical field of chip simulation, in particular to a TCL script-based waveform dump method, which comprises the following steps of: defining a system, a subsystem / submodule of the system, a dump level of the subsystem module and a dump level of the dump level according to a verification requirement of a chip in a simulation command line and / or makefile, and representing the dump level by using parameters; compiling an execution script based on a tool command language, the execution script being used for identifying the parameter representation of the simulation command line to analyze the verification demand of the chip, the execution script converting the verification demand into an analysis code; and adding a parameter for starting a UCLI command line mode in the simulation command line, and calling the analysis code in the UCLI command line mode to perform waveform dump. According to the application, after the verification demand of the chip is given through the simulation command line or the makefile, flexible selection of the dump waveform is realized.

The present disclosure provides a data processing method and device, electronic equipment and computer readable storage medium, the method comprising: obtaining configuration information to be processed, wherein the configuration information is information for indicating target data to be deleted; generating a target deletion execution instruction according to the configuration information; sending the target deletion execution instruction to a database storing the target data based on a preset data operation interface, the database being configured to precompile the target deletion execution instruction, wherein the preset data operation interface supports placeholders and precompilation of the target deletion execution instruction; and deleting the target data in the database according to the target deletion execution instruction. According to the embodiments of the present disclosure, the target data in the database can be conveniently and efficiently deleted.

A distributed graphical program development platform based on a lightweight reconstruction mechanism relates to the technical field of computers and comprises an upper computer and a lower computer. The upper computer comprises an equipment manager component, a development platform main body and a server which are mutually independent; wherein the equipment manager component is used for interacting field equipment and data information with the lower computer; the development platform main body is used for designing, managing, compiling and running a graphical program; the server provides role authentication, program version uploading / downloading of distributed development management and shared variable transfer functions for a user based on a C / S architecture; the lower computer comprises an Agent system service and is connected with the equipment manager component; the development platform can improve the program debugging and deployment efficiency.

The invention discloses a supply chain optimization method for beer preparation in advance. Comprising the following steps: calling related parameters configured by a system page as data input; calculating the net demand of the warehouse; calculating to-be-produced capacity of a factory; calculating a capacity gap, summarizing the to-be-produced capacity of each product to a supplier factory and a production line type, and respectively calculating capacity data of the factory and the production line type; production scheduling is simulated, and the forward moving amount is calculated; calculating the maximum stock quantity; sorting a stock order; sequentially distributing according to the sequence; the result is corrected, and the advance stock quantity is output. According to the method, the optimal supplier is found for the demand, the productivity resources are uniformly distributed, cross-district communication is reduced, and the manual compiling time is saved. And meanwhile, by accurately calculating the forward moving amount, accurate planning of stock preparation is realized, the order satisfaction rate is improved with a lower stock water level, the cost is saved, and the warehouse pressure is reduced. And the stock quantity of a single product is limited in a maximum stock quantity mode, so that the stock overstock risk caused by factors such as market fluctuation is reduced.

The invention discloses a file compiling method and device, electronic equipment and a storage medium, and relates to the technical field of data processing. According to the specific implementation scheme, compiling control parameters of a to-be-compiled file are obtained; creating a compiling thread according to the compiling control parameter, and adding the compiling thread to a preset thread pool; and compiling based on the unique identification information of the to-be-compiled file in each compiling thread. According to the embodiment of the invention, the file compiling time is shortened, the file compiling process is accelerated, repeated file compiling is avoided, and the file compiling efficiency is improved.

The present application belongs to the technical field of knowledge compilation and network reliability analysis, and particularly relates to a network reliability intelligent computing method and system for a logical decision graph, comprising: modeling a network system as a triple data structure composed of a network topology graph, a terminal node set and an edge availability probability set; determining a topology order of network nodes and network edges based on the triple data structure; constructing a full binary tree vtree with leaf nodes corresponding to network edges one by one according to the topology order; and compiling the network topology graph into a zero-suppression statement logical decision graph using the vtree, wherein the zero-suppression statement logical decision graph is used to represent a set of valid subgraphs that satisfy terminal node connectivity; and recursively calculating a reliability value of the network system based on the zero-suppression statement logical decision graph.

The invention discloses a web routing packet processing method based on an abstract syntax tree AST, and the method comprises the following steps: S1, loading a routing file of a web project based on a routing file loader, and obtaining a routing configuration file from a project directory; s2, slicing and grouping the routing source file; and S3, performing grouping starting and compiling on the items according to a slice grouping result. According to the method, firstly, the development source code is converted into an abstract syntax tree structure, then, the route source file is sliced, finally, the sliced files are arranged and grouped according to the sequence of the slices, and after grouping is completed, starting and compiling can be conducted according to the groups, so that unnecessary resource loading is reduced, and development efficiency is improved.

This invention discloses a SoC chip simulation verification method and system based on static and dynamic package separation. The method includes: acquiring simulation resources of the SoC chip to be verified; dividing the simulation resources into static and dynamic parts; the static part includes at least chip design code and basic verification environment components that do not need to be modified in the current verification stage, and the dynamic part includes at least verification test cases that need to be modified; encapsulating the static part into a static package and the dynamic part into a dynamic package; compiling the static package to execute the initialization simulation process, and saving the current initialization simulation state after the initialization simulation process is completed; compiling the dynamic package; loading the saved initialization simulation state, and executing the verification test cases in the dynamic package based on the restored initialization simulation state. This method avoids repeated compilation of large static resources due to modification of test cases, significantly shortens compilation time, and improves the verification efficiency and iteration speed of large-scale SoC chips.

The invention relates to a multi-server parallel compiling method and system based on large model aided decision making and a medium, and relates to the technical field of software compilation, the method comprises the following steps: obtaining a source code of a to-be-compiled project, and splitting the project into a plurality of independent compiling modules; based on the historical compilation data and the current server resource state, generating a configuration file containing a module allocation strategy through a large model; according to the configuration file, a compiling task is distributed to a plurality of servers through Jenkins Pipeline to be compiled in parallel; and collecting performance data in a compiling process, and feeding back the performance data to the large model to optimize a subsequent compiling strategy. Through large model intelligent analysis and a multi-server parallel compiling technology, the compiling time can be remarkably shortened, the resource utilization rate is improved, and dynamic optimization and self-adaptive adjustment of a compiling strategy are achieved.

The present application discloses a compiler code generation method for a cryptographic processor and related equipment. In the scheme, first, a data flow graph is obtained, and the data flow graph corresponds to multiple instructions; then, schedulable instructions are screened out from the instructions corresponding to the data flow graph, and a candidate cluster of each schedulable instruction is determined; then, a preset number of target instructions are determined from the schedulable instructions, and the cluster where the target instruction is located is determined based on the candidate cluster of each target instruction; the preset number is consistent with the number of instruction slots in a very long instruction; finally, based on the candidate register type of the operand in the target instruction and the cluster where the target instruction is located, register allocation is performed on the operand in the target instruction. The scheme is suitable for compiler code generation of a VLIW architecture cryptographic processor, and can reduce compilation time and improve the performance of the generated program.

The invention belongs to the technical field of compiler optimization, and discloses a node merging, compiling and optimizing system and method for a target architecture extension instruction, and the system comprises a node checking module, a node merging module, an instruction selection module and an error processing module; according to the instruction selection optimization method, operation nodes such as addition and displacement can be effectively recognized and combined, and the operation nodes are converted into the user-defined extension instruction nodes and finally mapped into the target machine instruction. By optimizing the node merging process in the Selection DAG, the number of generated instructions can be reduced, the execution performance of a program can be improved, and particularly for a SumerCore processor architecture depending on a user-defined instruction set, the hardware utilization efficiency can be remarkably improved.

The invention relates to the technical field of software development and compiling, and discloses an APP module firmware compiling and updating method, computer equipment and a storage medium. When it is monitored that a source code library changes, information stored last time and information stored this time are compared through combination of a list file and a JSON file; therefore, it can be ensured that only codes of the modules needing to be recompiled are compiled each time, unnecessary repeated compiling work can be effectively reduced, compiling time is shortened, meanwhile, the size of the OTA differential package is accurately controlled, and more efficient, rapid and user-friendly software updating experience is achieved.

The invention discloses an observation and diagnosis system for a database, and relates to the technical field of databases, the observation and diagnosis system comprises a flow monitoring module, a flow dispersion module, a debugging module and an emergency module, the flow dispersion module is connected with the flow monitoring module through signal transmission, and the debugging module is connected with the flow monitoring module through baseband transmission. The emergency module is connected with the flow monitoring module through wireless transmission, and a monitoring tool, a log analysis tool and a network data packet analysis tool are arranged in the flow monitoring module. By designing the flow monitoring module, the function of monitoring the data volume is achieved, the problems that hardware resource bottlenecks are not found in time, internal resources of a database are unreasonably used and hidden hardware faults are not easy to find are solved, the change of the data volume can be found in time, performance reduction caused by too large data volume is avoided, and the service life of the database is prolonged. The security index of the database is improved, and the resource utilization rate is improved.

The invention discloses a PLC incremental compiling method of a BS architecture based on a PLCope standard, which comprises the following steps: initializing a PLC programming environment, establishing communication connection between a compiling server and a client IDE, and loading a relevant library and a configuration file of the PLCope XML standard; the client IDE formats a user program into a PLCopen XML structure and submits a PLC program compiling request, and a compiling server analyzes program modification content and a program dependency relationship by using a PLCopen standard format; and the compiling server traverses the user program again according to the dependency relationship, determines the content needing to be recompiled in the current project, compiles the content to obtain a target file generated by incremental compiling, links the target file with the target file of the unmodified part to generate a final execution file, and stores the final execution file. And sending the file as a response of a compiling request to a client IDE, downloading the file into a connected PLC device, starting operation, and completing incremental compiling. According to the invention, the PLC programming and debugging efficiency is improved, and the consistency and stability of the system are ensured.