96results about How to "Save compilation time" patented technology

The invention discloses a software packaging and publishing management method. According to the method, after iterative content of a version is confirmed, a corresponding version number is selected during packaging, only a needed script is generated, the content needing to be published is precisely controlled, and codes which are not tested are prevented from being deployed into a formal environment; when script packaging is executed, components with source codes not updated are not recompiled, therefore, only changed parts are compiled, compiling time is shortened, and incremental compiling is realized; based on version tracing of historical version logs, a log directory is generated every time packaging is performed; and when a user needs to generate a historical version of a certain time, logs of the needed historical version are selected, a packaging script is selected from the logs, and a script command is executed to generate a needed package. In this way, it is not needed to back up generated packages every time packaging is performed, only the package generated this time is stored, therefore, storage space is reduced, and maintenance of the historical version is realized with little hard-disk space.

The invention provides a mobile business module componentization configuration method. The method comprises the steps of enabling module source codes to be independent of a project; configuring gradlescripts for independent compilation, debugging and running of modules; performing isolation processing on the codes; and performing optimization control on a version. The coupling degree of the codemodules can be effectively reduced, so that a code framework is clearer, and the modules can be subjected to independent development, running and debugging with the main project; and the modular compilation can effectively shorten the compilation time. The invention furthermore discloses a mobile business module componentization configuration system.

The invention relates to a method and a device used for processing a source file, and provides a method used for processing the source file to generate an object file. The method comprises the following steps: obtaining a header file referred by the source file; responding when the source file calls data symbols defined in the header file, and creating the indicators of the definitions of the data symbols, wherein the definitions of different data symbols correspond to different indicators; and adding the indicator into a compiling result obtained by compiling the source file to generate an object file. The invention also provides a method used for processing the source file. The method comprises the following steps: responding when the header file referred by the source file is updated, and looking up the definition of the data symbol called by the source file from the header file; creating the indicator of the definition of the data symbol; and responding when the indicator is matched with the indicator in the object file generated from the source file, and notifying that the source file does not need to be re-compiled. The method and the device can record a dependency relationship between the source file and the header file, and an amount of the source files which need to be re-complied is lowered on the basis of the dependency relationship.

The invention discloses a code compiling method, host computer and system. The method comprises the following steps of: decomposing a code to be compiled into a plurality of module codes; instructing each compiling extension set in a plurality of compiling extension sets to acquire a module code respectively and compile the module code into an executable file; and when all module codes are compiled successfully, selecting one compiling extension set from the plurality of compiling extension sets and controlling the compiling extension set to link executable subfiles corresponding to all the module codes into executable files. Compared with the prior art, the method provided by the embodiment of the invention has the advantages that: the compiling time is greatly saved, the compiling speed is increased, the software developing period can be shortened, and the software developing cost is lowered.

The invention relates to a standardized maintenance method for a reconstruction and extension information point table of a running substation. The method is characterized by comprising the following steps of compiling an information access application form according to running substation transformation range and generating regularized reconstruction and extension equipment monitoring information points according to the existing intervals and an equipment type structure; generating reconstruction and extension intervals and equipment monitoring information point numbers; and exporting the generated information point table and carrying out flow joint debugging check on the information point table. According to the method, by utilizing a way of constructing the substation intervals and equipment thereof through the structured organization, and a complete rule base, the reconstruction and extension information point table is quickly generated, and meanwhile, filing retention of the point table of each edition in each stage is formed to guarantee the system to view the data of the information point table in each stage at any time; a convenient and efficient support is provided for the maintenance work of the reconstruction and extension information point table of the substation, normalization and standardization of monitoring of the information point table are guaranteed, the check period is shortened, the work quality and the work efficiency are improved, and the equipment running safety is guaranteed.

The invention provides a rapid method to accelerate the calculation of an output value eqcID corresponding to each chunk of phase 0. The method comprises the steps of input data processing, endpoint sorting processing and rule pool iteration processing. Through employing the sorting and using a mode of rule pool iteration, the query result eqcID corresponding to the chunk of phase 0 is evaluated. According to the above method, the characteristics of access control entries are fully utilized, the related information is dug deeply, the steps of eqcID calculation and compilation time of index are greatly reduced, the come into effect of a configuration access control list rule is accelerated, and the function of network equipment is protected well.

The invention discloses a file dynamic loading method and device, relates to the technical field of computers, and mainly aims to improve the dynamic loading efficiency of the file. According to the main technical scheme, the method comprises: loading a program file in a preset virtual machine, the preset virtual machine being used for loading an original program file, and code compiling does notneed to be conducted on the original program file; and constructing a program file object by analyzing the information in the program file. The method and the device are mainly used for dynamically loading the program file.

The invention discloses an application program code compiling method. The application program code compiling method comprises the following steps: obtaining a source code of an application program; traversing the source code to judge whether the source code comprises a Flutter framework or not; if the source code does not comprise the Flutter framework, adopting a first compiling mode to compile the source code; if the source code comprises a Flutter framework and the Flutter framework is a redundant Flutter framework, removing the redundant Flutter framework from the source code; and adoptingthe first compilation mode to compile the source code with the redundant Flutter framework removed. Meanwhile, the invention discloses an application program code compiling device and equipment and astorage medium. The redundant Flutter framework in the application program code compiling process is removed, so that the application program code compiling process can select the required compilingmode, meanwhile, the compiling time is shortened, and the efficiency is improved.

The invention discloses a distributed authoring and versioning method and a distributed authoring and versioning system, relating to the field of information processing and being used for solving the problem of long authoring and versioning time caused by low software code authoring and versioning efficiency. The method provided by the invention specifically comprises the following steps: independently determining a mode of a to-be-authored and versioned code segment needing being authored and versioned by adopting each slave server, and averagely sharing time consumption of allocating tasks to each slave server so as to increase the authoring and versioning efficiency of software and shorten the authoring and versioning time. The embodiment of the invention is mainly used in a process of developing software.

A glass fine grinding machine comprises a frame (1), a work platform (11) and a processing mechanism support (2). A linear motor type Y axial adjustment mechanism (3) is arranged between the frame (1) and the work platform (11), and the processing mechanism support (2) is provided with a linear motor type X axial adjustment mechanism (4), a Z axial feeding mechanism (5), a grinding unit (6), cutters (61) and a control system (7). By means of the improved scheme, the glass fine grinding machine can avoid the influence of water mist on a processing device to the largest extent so as to ensure processing accuracy. Simultaneously, the system has the advantages of being high in processing efficiency and free of requirement for frequently replacing the cutters so as to greatly improve working efficiency.

The invention relates to the technical field of software, and discloses a software product compiling method and device. By means of the software product compiling method and device, the compiling process can be optimized, the compiling time and resource consumption can be reduced, and the compiling efficiency can be improved. The software product compiling method includes the steps that codes of multiple software products are received, wherein the code of each software product comprises a public code part and a software product specific code part; the public code part is compiled to generate a public code part compiling result; the software product specific code parts of the software products are compiled respectively to generate software product specific code part compiling results of the software products respectively; the software product specific code part compiling results of the software products are combined with the public code part compiling result to generate code compiling results of the software products.

The invention provides a business project calling method and device and an electronic device, and relates to the technical field of computers. The method and device are used for an application including a main project and multiple business projects. The business projects are integrated into the main project. Each business project includes at least one functional module, the at least one functional module can independently implement a business. The method includes the steps that a business execution request is obtained, wherein the business execution request includes identification of the business; according to the identification, the functional module for implementing the business is searched in the main project; the functional module is called and executed. Therefore, coupling between the business projects can be reduced, and reuse of the business projects is strengthened. When the code of one business project is updated, people do not need to compile the whole application again, so that the compiling time of each business project is shortened, and the collision probability is reduced.

The invention provides an Android source code compiling method and an Android source code compiling system. The Android source code compiling method comprises the steps of copying a binary file generated through compiling a third party source code under the compilation output directory of an original Android source code to a preset receiving directory; copying the binary file generated through compiling the third party source code under the receiving directory to a new compilation output directory established for compiling the new Android source code; and modifying the compilation configuration of the third party source code, thus invalidating the compilation of the third party source code when compiling the new Android source code, and packaging the software version corresponding to the new Android source code after the new Android source code is compiled. The Android source code compiling method can greatly save compiling time and improve compiling efficiency, and is simple to operate and high in practicability.

The invention relates to the technical field of ferrous metallurgy information technology, and particularly relates to a combinatorial optimization method of steel coil stacking of a hood-type annealing furnace. According to the characteristics of an annealing process of a hood-type annealing furnace, based on the analysis of the effect of steel coil overall dimensions (external diameter, width, thickness, etc.) and steel grades on annealing time and the restriction of various constraint conditions, and aiming at the optimization objects of minimizing stacking number and maximizing furnace stage production efficiency, the invention establishes a mathematical model for the optimization of hood-type furnace stacking, and provides a hybrid genetic algorithm (FGSA) combining algorithms of a first fit decreasing algorithm (FFD), a genetic algorithm (GA), and a simulated annealing algorithm (SA) for the solution of the model. The method can realize the informatization and the automation of hood-type furnace annealing production, reduce the labor intensity of scheduling personnel, increase the production efficiency of production factories, and has the effect of energy saving and consumption reduction.

The embodiment of the invention discloses a training model implementation method and device and a computer readable storage medium. The method comprises the steps that a training program loads a dynamic library generated by a service algorithm logic layer; And during forward propagation and backward propagation calculation, a forward propagation program and a backward propagation program of the dynamic library is called for training through a forward propagation interface and a backward propagation interface to obtain a training model. The training program and the service algorithm logic layerare decoupled, the training program and the service algorithm logic layer can run independently, the training program can load the service algorithm logic layer to run, and respective development andmaintenance are facilitated; Compilation and operation only involve service algorithm logic layer codes, the compilation time is saved, and the version development efficiency is improved.

An SOC (System on a Chip) software and hardware collaborative simulation verification method based on network communication protocol is provided, which comprises the steps of: firstly, constructing a test platform end and a test excited end; and then carrying out data exchange through a self-explanatory data packet format, wherein the test platform end is a network server, including verilog design, System C model and a server packing / unpacking module written in C++ under the operation of a third-party simulator; the test excited end is a network client, including a test software and a client packing / unpacking module. The self-explanatory data packet format includes a reading / writing format on a bus, a reading / writing format of a VPI (Virtual Path Identifier) and simulative behavior control. In the invention, the compiling of the test excitation is simplified and the compiling time is saved, and the simulation velocity is increased and the test completeness of verilog design is improved.

The embodiment of the invention discloses a management method and device of a system resource, relates to the field of communication systems, and solves the problem that the system resource utilization efficiency is very low on an Android platform. The method comprises the following steps of: firstly, generating a fixed identity identification number of a system resource provided by an Android system, and when a new resource is increased, denominating the newly increased source according to English letter marshaling sequence characteristics in a preset mode; and finally generating an identity identification number of the newly increased source based on the resource identity identification number automatic generation principle of the Android system and the name of the newly increased resource, and placing the identity identification number of the newly increased resource behind the identity identification numbers of all system resources. The management method and device provided by the invention are suitable for the field of the communication systems.

An embodiment of the invention provides a C program compiling method and a C program compiler. The C program compiling method includes subjecting a C program to lexical analysis, grammatical analysis, semantic analysis and intermediate code generation sequentially, allocating the C program subjected to semantic analysis and intermediate code generation on at least two threads by taking functions as units so as to perform intermediate code optimization respectively; performing target code generation on the C program subjected to intermediate code optimization. The C program compiling method and the C program compiler have the advantage that time consumption in the rear-end phase can be reduced, so that C program compiling efficiency is improved.

The invention discloses a service choreography method and device, and relates to the technical field of computers. A specific embodiment of the method comprises the following steps: acquiring preset service configuration information according to an interface name and a service input parameter in a calling request; wherein the service configuration information comprises service mapping information, service calling information and a service interface execution sequence; obtaining a corresponding service processing script according to a script address in the service mapping information, grouping service interfaces of the service calling information according to a service interface execution sequence, and generating a task queue by taking the service interfaces belonging to the same group as task nodes; according to a service interface execution sequence of service interfaces in the task nodes, pulling the task nodes from the task queue, and executing the service interfaces of the task nodes to obtain a return result; and assembling the returned result by using the service processing script, and returning an assembling result. According to the method, the flexibility of service calling is improved, the development cost is reduced, and the product updating period is prolonged.

The embodiment of the invention discloses a component method, a device, an apparatus and a storage medium of an application program. The method comprises the following steps: acquiring the interface layer information to be called by the first component; Determining the implementation layer information of the second component according to the interface layer information to be called by the first component and the mapping relationship between the interface layer information of each component and the implementation layer information; Transmitting the implementation layer information of the secondcomponent to the first component for the first component to call the implementation layer according to the implementation layer information; Wherein the first component and the second component respectively belong to different functional modules of the application program. The embodiment of the invention realizes decoupling between components through a service center to avoid circular dependencyerrors; By splitting into components, it can reduce compiling time, improve development efficiency and reduce the difficulty of collaborative development.

The invention discloses a method and an apparatus for increasing the compilation speed of an android system, and belongs to the technical field of android software development. The method comprises the steps of obtaining a feature code of a current source code file in a current source code directory, and in combination with the feature code of the current source code file and stored feature codesof historical source code files in multiple historical source code directories, determining a to-be-compiled module and a non-compiled module; according to the non-compiled module and stored historical compiled files in multiple historical compiled destination folders, determining a target historical compiled file corresponding to the non-compiled module, and adding the target historical compiledfile to a target position of a current compiled destination folder; and according to the to-be-compiled module, generating a compiled module list, and according to the compiled module list and the target historical compiled file, compiling the current source code file to generate a current compiled file. The quantity of modules needed to be compiled can be reduced, so that a large amount of compilation time is saved.

The invention relates to an FPGA layout and wiring method with soft error sensing. The method comprises the following steps: firstly, finishing analysis and modeling of soft errors of wiring resources in an FPGA; on the basis of research on a soft error model, introducing an anti-radiation factor in the layout and wiring process, and improving the soft error sensing capacity of the layout and wiring method; aiming at the problem of slow convergence caused by a random process and iteration in the layout process, optimizing the layout process by using a direct process enhanced learning method, so that the layout process is more intelligent and efficient; in order to solve the problem that the wiring speed is low, carrying out recursive division on wire nets with different characteristics on the basis of a novel rewiring strategy, and then adopting different parallel wiring strategies to complete the parallel wiring process. The layout and wiring method has a soft error sensing capability, can relieve the influence on the circuit performance caused by soft errors of wiring resources in the FPGA, and can reduce the system compiling time on the basis of increasing the intelligent degree of the system.

The invention provides a method and equipment for compiling an operating system. The method comprises the following steps of: analyzing a source code data packet to be compiled into a compiling dependency table and a compiling product table; creating a compiling sequence table, and adding dependency items in the compiling dependency table into the compiling sequence table based on the compiling product table; sequentially compiling the plurality of packages in the compiling sequence table according to a sequence based on a compiling environment, and judging whether each time of compiling succeeds or not; and in response to successful compiling, compiling the next packet until compiling is completed. By using the scheme of the invention, the compiling time of the operating system can be greatly reduced, and the risk of compiling failure is reduced.

The invention discloses a distributed compiling method and device and a storage medium, the method is applied to a client, and the method comprises the following steps: receiving a compiling task of a to-be-compiled file; initiating an application of distributed compiler resources to a server according to the to-be-compiled file, and receiving a resource allocation result fed back by the server; dividing the compiling task into a plurality of compiling sub-tasks according to the resource allocation result; and sending the compiling sub-task to a distributed compiler specified by the resource allocation result for compiling processing, and receiving a compiling result returned by the distributed compiler. By means of the mode, the current resource condition of each distributed compiler can be inquired, and the compiling tasks are reasonably divided and distributed according to the current resource condition so as to ensure that the compiling tasks can be completed in time.

The invention discloses a visual configuration programming method and system. The method comprises the steps: recognizing programming logic set by a user through a visual interface of configuration software; and converting the programming logic into script program codes which can be executed by the controller. By adopting the technical scheme of the invention, the universality and debugging efficiency of the configuration software can be improved.

The invention provides a data compiling method and a map compiler. The method is applied to the map compiler. The map compiler comprises a plurality of compiling modules, and a corresponding self-recovery node is arranged at an initial position of each compiling module. The method comprises the steps of: detecting abnormal information in the compiling process of the map compiler in real time; when the abnormal information is detected, according to the abnormal information, determining a compiling module which is abnormal; controlling the compiling module which is abnormal to carry out self-recovery according to initial parameters stored in the corresponding self-recovery node; after self-recovery of the compiling module which is abnormal is completed, repairing the compiling module which is abnormal; and after repair on the compiling module which is abnormal is completed, according to a control instruction input by a user, controlling a target compiling module to continue to execute the compiling process according to compiling data and the initial parameter which are stored in the corresponding self-recovery node. According to the data compiling method and the map compiler which are provided by the invention, for the condition that the compiling module is abnormal, compiling time is greatly shortened, and data compiling efficiency is improved.

The invention provides a method for simulating a virtual interface designed by a logic system and related equipment. The method comprises the following steps: receiving description of a virtual interface in the logic system design, wherein the virtual interface is used for exchanging data with a physical interface of the logic system design; based on the description of the virtual interface, generating a handle command associated with the virtual interface, the handle command being used for executing an operation associated with the virtual interface when the logic system design is run; and based on the handle command associated with the virtual interface, simulating the logic system design.

The invention provides a file compilation method and device. The method comprises steps as follows: when a compilation order is received, a first shared library file on which a to-be-compiled executable program file depends is acquired, and a second shared library file on which the first shared library file depends is acquired; the second shared library file is taken as a dependent file to be added to a dependency list in Makefile of the executable program file; when the condition that the generation time of the dependent file is later than that of the executable program file, the executable program file is compiled again. According to the technical scheme, compilation time can be shortened, compilation resources are saved, and complexity of compilation is reduced.

The invention provides a memory coupling compiling method and system for a reconfigurable chip. The memory coupling compiling method comprises the following steps: acquiring the periodicity of a DFG data flow diagram; obtaining a linear conversion vector of the periodicity through the mapping time difference; and judging whether a linear array of the linear conversion vector can be obtained through a heuristic algorithm or not, obtaining a memory mapping result according to a judgment result or through the current DFG data flow diagram, and obtaining and adjusting the current DFG data flow diagram until the linear array is obtained. According to the method and the device, each node in the DFG data flow diagram is adjusted, so that the requirement of obtaining the linear array is met, the compiling time is greatly shortened, and the compiling experience of a user is very strong. The reconfigurable acceleration chip is high in practicability, can be used, and has extremely high reusability for programmable devices.