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Integrated clock circuit

A technology of integrated circuits and clock integrated circuits, which is applied in the direction of reliability improvement and modification, and can solve the problems of increased grain area and cost

Active Publication Date: 2014-08-06
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In order to isolate the impact of power supply fluctuations on the clock signal, these relatively complex buffer circuits cause a substantial increase in die area and cost

Method used

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  • Integrated clock circuit
  • Integrated clock circuit
  • Integrated clock circuit

Examples

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Embodiment Construction

[0062] figure 1 A block schematic diagram of an integrated circuit clock circuit with tolerance to variations such as temperature, ground voltage, or supply voltage is shown.

[0063] The integrated circuit clock circuit is usually a one-loop structure with a timing circuit 102 , a level switching circuit 104 and a latch circuit 106 . The latch circuit latch circuit 106 generates a feedback signal from the latch circuit latch circuit 106 to the sequential circuit 102 and a clock output signal 110 . The timing circuit 102 switches between the two reference signals according to a time constant. This time constant thus determines the timing of the integrated circuit clock circuit. A typical example of a time constant is an exponential time constant, which characterizes the rise and fall times of an RC circuit or RL circuit. The level switching circuit monitors the output of the timing circuit 102 and changes its output according to whether the timing circuit 102 is high or low...

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Abstract

The invention provides an integrated clock circuit with tolerance capacity for temperature change, grounding voltage change or power voltage change. The modified integrated clock circuit can tolerate one or various changes including the temperature change, the grounding voltage change and the power voltage change in different embodiments.

Description

[0001] This application is a divisional application, the application number of the parent case: 200910260481.9, the application date: December 15, 2009, and the name: integrated circuit clock circuit. technical field [0002] The present invention relates to integrated circuits with clock circuits that are tolerant to variations such as temperature, ground noise, power supply noise, and the like. Background technique [0003] The operation of the clock circuit of an integrated circuit will vary with factors such as temperature, ground noise, and power supply noise. Since these variations will affect the final timing of the output clock signal, a number of studies have been conducted to address this issue and produce a more uniform output clock signal in the presence of the above variations. [0004] For example, US Pat. No. 7,142,005 to Gaboury uses a buffer circuit with an active load, independent bias circuitry, and bias circuitry to isolate the clock signal from power flu...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/003
Inventor 陈重光洪俊雄陈汉松
Owner MACRONIX INT CO LTD