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Integrated mechanism for suspension and deallocation of computational threads of execution in a processor

A technology of processors and digital processors, applied in the direction of machine execution devices, calculations, program control design, etc.

Inactive Publication Date: 2013-01-16
MIPS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Another problem that exists in multithreaded processors is that the scheduling principle makes a thread keep running until it is blocked by some other resource, while a thread that is not blocked by any resource still needs to cause the processor to switch to other threads

Method used

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  • Integrated mechanism for suspension and deallocation of computational threads of execution in a processor
  • Integrated mechanism for suspension and deallocation of computational threads of execution in a processor
  • Integrated mechanism for suspension and deallocation of computational threads of execution in a processor

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Embodiment Construction

[0079] According to a preferred embodiment of the present invention, a processor architecture includes an instruction set, and the instruction set includes features, functions, and instructions capable of generating multi-threaded operations on a compatible processor. The present invention is not limited to any specific processor architecture and instruction set, but can be roughly classified into the well-known and referenced MIPS architecture, instruction set and processor technology (in a word, MIPS technology). And the embodiments described in detail in addition to the present invention can also be classified as MIPS technology. More information on MIPS technology, including the documents referenced below, is available from MIPS Technology, Inc. (Mountain View, California) and its website www.mips.com (the company's website).

[0080] References to "processor" and "digital processor" include any programmable device (for example, microprocessor, microcontroller, digital s...

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Abstract

A mechanism for processing in a processor enabled to support and execute multiple program threads includes a parameter for scheduling a program thread and an instruction disposed within the program thread and enabled to access the parameter. When the parameter equals a first value the instruction, when issued by a program thread, reschedules the program thread in accordance with one or more conditions encoded within the parameter.

Description

[0001] This application is a divisional application of the Chinese invention patent application with the application number 200480024800.1, the application date is August 26, 2004, and the invention title is "an overall mechanism for suspending and releasing computing threads in the processor during execution" . [0002] Related applications cross-referenced with the present invention [0003] This application claims priority from the following applications: [0004] (1) U.S. provisional application No. 60 / 499,180, filed on August 28, 2003, titled "Multithreading Application Specific Extension" (attorney number P3865, inventor Kevin Kissey Kissell (Kevin D. Kissell, Express Mail No. EV 315085819US), [0005] (2) U.S. Provisional Application No. 60 / 502,358, filed September 12, 2003, titled "Multithreading Application Specific Extension to a Processor Architecture" ( Attorney No. 0188.02US, Inventor Kevin D. Kissell, Express Mail No. ER 456368993US), and [0006] (3) U.S. Prov...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/30G06F9/38G06F9/48G06F9/45
CPCG06F9/4881G06F9/3851G06F8/4442G06F9/3009
Inventor 凯文·基塞尔
Owner MIPS TECH INC