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Layout Design Method and Layout Structure for Reducing DC Offset Voltage of Cascaded Amplifier Circuit

A technology of DC offset and bias voltage, which is applied to improve the amplifier to reduce temperature/power supply voltage changes, adjust electrical variables, instruments, etc., to achieve the effect of reducing DC offset voltage

Active Publication Date: 2016-03-23
ZHUHAI JIELI TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The DC offset voltage of a few mv will become hundreds of mv to the output, which is unacceptable in most applications

Method used

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  • Layout Design Method and Layout Structure for Reducing DC Offset Voltage of Cascaded Amplifier Circuit
  • Layout Design Method and Layout Structure for Reducing DC Offset Voltage of Cascaded Amplifier Circuit
  • Layout Design Method and Layout Structure for Reducing DC Offset Voltage of Cascaded Amplifier Circuit

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Experimental program
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Effect test

Embodiment 1

[0024] The cascaded amplifier involved in this embodiment is composed of two inverting amplifiers. In the layout design process of this embodiment, try to make the magnitude and direction of the DC offset voltage of operational amplifier A and operational amplifier B close to each other, so as to achieve the result of mutual cancellation. , and finally realize the minimum output DC offset voltage of the cascaded amplifier.

[0025] A typical op amp circuit, such as op amp A (op amp B is the same as op amp A), is mainly composed of: A input tube, A current mirror 1 (PMOS), A current mirror 2 (NMOS), A bias voltage circuit and A output circuit. Among them, the matching degree of the input tube, the current mirror 1 and the current mirror 2 determines the magnitude of the output DC offset voltage of the operational amplifier.

[0026] combine image 3 As shown, the layout design method provided in this embodiment adopts the approach of direct close matching, which mainly includ...

Embodiment 2

[0029] combine Figure 4 As shown, the difference between the second embodiment and the first embodiment is that the layout design method provided by the second embodiment adopts the method of centrosymmetric matching, which mainly includes: the bias voltage circuit (301, 303) of the operational amplifier A and the operational amplifier B Place the bias voltage circuit (401, 403) close to each other; place the current mirror 1 (304, 307) of the op amp A and the current mirror 1 (404, 407) of the op amp B in a center matching method; place the op amp A input tube (305, 308 ) and op amp B input tubes (405, 408) are placed by center matching; the op amp A current mirror 2 (306, 309) and op amp B current mirror 2 (406, 409) are placed by center matching.

[0030] Such as Figure 4 As shown, the layout structure of the cascaded amplifier provided in Embodiment 2 is as follows: the bias voltage circuit (301, 303) of the operational amplifier A and the bias voltage circuit (401, 403...

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Abstract

The invention discloses a layout design method and a layout structure for reducing a direct-current offset voltage of a cascade amplification circuit. The layout design method is mainly characterized in that the values and directions of direct-current offset voltages of operational amplifiers A and B are designed to be closer. The invention has the benefits as follows: the direct-current offset voltage of the cascade amplification circuit is effectively reduced through the new layout design method; and the layout design method and the layout structure can be applied to not only a two-stage cascade amplifier circuit but also a multi-stage cascade amplifier circuit.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a layout design method and a layout structure of a cascaded amplifier circuit. Background technique [0002] In the CMOS process, an operational amplifier that has not been calibrated has a DC offset voltage of about several mV. Where high magnification is required (gain greater than 100). The DC offset voltage of a few mv will become hundreds of mv to the output, which is unacceptable in most applications. [0003] figure 1 It is a circuit diagram of a cascaded amplifier, which consists of two stages of inverting amplifiers. In the ordinary layout design method, the layout of op amp A and op amp B are arranged independently, such as figure 2 , their DC offset voltage has a certain randomness, and the following situations may occur: [0004] 1. The DC offset voltage of op amp A is positive, and the DC offset voltage of op amp B is also positive. [...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03F1/30G05F1/56
Inventor 黄海涛张宝月
Owner ZHUHAI JIELI TECH