Dual Gate Flash

Abstract

The invention relates to a dual-gate flash memory, and provides a method for manufacturing a split-gate memory unit with a fin structure between memory gate stacks and selection gates. Embodiments include a first channel region under the memory gate stack and a second channel region under the select gate.

Description

technical field [0001] The invention discloses a flash memory with improved data retention and unit durability. In particular, the present invention relates to a flash memory for 32 nanometer (nm) technology and beyond. Background technique [0002] Split-gate flash memory technology has been widely used in low-to-medium density applications. However, existing split-gate flash memory structures are designed to share the same channel for read, erase, and program (or write) operations, which poses serious reliability issues such as data retention and cell endurance . Efforts have been made to improve data retention and enhance durability features such as Figure 1A The structure shown, including source region 101, drain regions 103 and 105, trench dielectric 107, channel regions 109 and 111, floating gate 113, and control gate 115, utilizes separate channel region 109 and 111 for reading and programming. Such as Figure 1B and Figure 1C As shown, the read operation uses...

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Problems solved by technology

Therefore, both erase and read operations are performed on the same channel, subjecting the read-designated channel region to the degradation caused by the erase

The write-assigned channel may also experience gate disturbance during read operations, resulting in undesired data leakage due to stress-induced leakage current (SILC)

In addition, if Figure 1A structure shown during programming (e.g., C due to dual channel TOT rising) yields a low gate coupling ratio (e.g., C FG / C TOT ), which means that the programming efficiency is reduced

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