A Graphical Approach to Reducing Bonding Voiding

Abstract

The invention relates to a manufacturing technology of a semiconductor device, in particular to a graphic method for reducing bonding cavities, which solves the problems of high probability of producing bonding cavities and overlarge thermal stress existing in the conventional wafer bonding technology. The graphic method for reducing the bonding cavities is implemented through the following steps: (1) selecting a GaAs substrate; growing an N-GaAs layer on the GaAs substrate; growing a quantum well layer on the N-GaAs layer; growing a P-GaP layer on the quantum well layer; (2) manufacturing a current diffusion layer on the P-GaP layer; (3) manufacturing an ohmic contact layer on the current diffusion layer; (4) manufacturing graphics on the ohmic contact layer by using a photo-etching method; (5) selecting a base plate; manufacturing a material bonding layer on the base plate; (6) manufacturing a material reflecting layer on the material bonding layer; (7) bonding the material reflecting layer with the ohmic contact layer; (8) removing the GaAs substrate by using a chemical corrosion method. The graphic method is applicable to manufacturing the semiconductor device.

Description

technical field [0001] The invention relates to semiconductor device manufacturing technology, in particular to a patterning method for reducing bonding voids. Background technique [0002] Continuously optimizing the parameters and structures of semiconductor devices to obtain better performance of semiconductor devices has always been the goal pursued by the field of semiconductor devices. Semiconductor devices are usually made of a variety of semiconductor materials, so only by combining the excellent characteristics of various semiconductor materials can semiconductor devices achieve better performance. At present, when a semiconductor device is manufactured using a variety of semiconductor materials with lattice matching, the semiconductor device is mainly manufactured by epitaxial growth on a substrate. However, when using various semiconductor materials with high lattice mismatch and large differences in thermal expansion coefficients to manufacture semiconductor dev...

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