Integrated circuit underfill scheme
A technology for integrated circuits and underfills, applied in circuits, electrical components, electrical solid devices, etc., which can solve problems such as contamination of stacked packages, low additional cost, width/height control accuracy, etc.
Active Publication Date: 2014-05-14
TAIWAN SEMICON MFG CO LTD
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- Application Information
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Problems solved by technology
However, the underfill material can overflow the target area and the overflow can contaminate the package-on-package (PoP) pads for solder bumps above the substrate
Some packages use damming material outside the underfill to stop spillage, resulting in additional cost and lower width / height control accuracy due to soft liquid damming material and tool tolerances
Method used
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[0029] The making and using of various embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the disclosure.
[0030] Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purposes of brevity and clarity only and does not in itself dictate a relationship between the various embodiments and / or structures discussed. Also, in the following disclosure, the formation of one part on another part, the connection of one part to another part and / or the coupling of one part to another part includes embodiments in which the parts are formed in direct contact , and may also include embodiments in which additional parts are ...
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An integrated circuit includes a substrate having at least one depression on a top surface. At least one solder bump is disposed over the substrate. A die is disposed over the at least one solder bump and electrically connected with the substrate through the at least one solder bump. An underfill surrounds the at least one solder bump and is formed between the substrate and the die. The at least one depression is disposed around the underfill to keep any spillover from the underfill in the at least one depression. The invention also provides an integrated circuit underfill scheme.
Description
[0001] priority [0002] This application claims the benefit of US Provisional Patent Application No. 61 / 720,266, entitled "Integrated Circuit Underfill Scheme," filed October 30, 2012, the entire contents of which are hereby incorporated by reference. technical field [0003] The present disclosure relates generally to integrated circuits and, more particularly, to underfill schemes. Background technique [0004] In some integrated circuit packages, an underfill material is used to fill the space between the chip and the substrate on which the chip is mounted via solder bumps. The underfill protects the solder bumps from moisture or other environmental hazards, provides additional mechanical strength to the assembly and compensates for differences in thermal expansion between the chip and substrate. However, the underfill material can overflow the target area and the overflow can contaminate the package-on-package (PoP) pads for solder bumps above the substrate. Some pack...
Claims
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IPC IPC(8): H01L23/13H01L21/58
CPCH01L21/563H01L23/13H01L23/49811H01L23/49827H01L23/49833H01L24/45H01L24/48H01L24/73H01L2224/16225H01L2224/32225H01L2224/45124H01L2224/45144H01L2224/45147H01L2224/48091H01L2224/48227H01L2224/73204H01L2224/73265H01L2224/83385H01L2225/1023H01L2225/1058H01L2924/00014H01L2924/15311H01L2924/15331H01L2924/00012H01L2924/00H01L2224/45015H01L2924/207H01L21/4853H01L23/3107H01L23/3142H01L24/17H01L24/32H01L24/49H01L24/81H01L25/0657H01L25/50H01L2224/13111H01L2224/13147H01L2224/16227H01L2224/48106H01L2224/49107H01L2224/81192H01L2225/0651H01L2225/06517H01L2225/0652H01L2225/06572H01L2924/014H01L2924/14
Inventor 梁世纬吕俊麟吴凯强杨青峰刘明凯缪佳君王彦评
Owner TAIWAN SEMICON MFG CO LTD