Data queue dequeue control method and device

Abstract

Disclosed are a method and apparatus for managing and controlling the dequeuing of a data queue. The method comprises: a queue scheduling instruction is received, and the first address of the queue and the dequeuing sub-pointer are obtained and combined into an absolute address; the child node information of a dequeuing node is obtained according to the order of the absolute address and written into the recombined queue; the child node information of the next dequeuing node is prefetched crosswise according to the parity order of the dequeuing node and written into a parity linked list, and the packet tail identification of the next dequeuing node is prefetched; a start flag is monitored, and the scheduling number of a data packet is written into the sequenced queue sequentially according to the arriving order of the start flag; and the child node information of the dequeuing node in the recombined queue is fetched sequentially according to the order of the scheduling number, and pointing to the corresponding data packet storage location, the data packet dequeuing instruction is sent.

Description

technical field [0001] The invention relates to the technical field of data processing, in particular to a method and device for managing and controlling data queue dequeue. Background technique [0002] With the continuous growth of network services and capacity, the requirements for the processing capability of traffic control chips are getting higher and higher. When the flow control chip implements large-scale queue control, it is more common to use a linked list to store the data message in the off-chip DDR (Double Data Rate) memory, and the index address corresponding to the data message is stored in the form of a queue. In the off-chip QDR (Quad Data Rate, 4 times data magnification) memory, during dequeue operation, the index address is obtained, and the data message corresponding to the index address is read out to complete the dequeue of the data message. [0003] The management and control of the queue is mainly the management and control of the message storage, ...

AI Technical Summary

Problems solved by technology

If the traditional single-linked list structure is adopted, the read and write delay of the off-chip QDR memory will cause the single-queue dequeue to fail to meet the speed requirements for entering and exiting the queue, and will occupy a large amount of SRAM (Static Random Access Memory, static random access memory) resources. Using FPGA ( When Field-Programmable Gate Array, field programmable gate array) is implemented, it is a huge challenge for both device pin allocation and layout and routing; if a multi-linked list structure is used, there is still the disadvantage that a large number of SRAM resources are occupied, and it is implemented using FPGA , the device pin assignment and layout are more difficult than the singly linked list scheme

At the same time, the method of implementing queue control by using a singly linked list is mainly to store the address pointer of each node in the queue in the linked list, and the address of the next node can only be obtained after reading out one node. Considering the read delay of the QDR memory, it cannot Meet the rate requirements for dequeue processing

Images