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Automated Design Layout Pattern Correction Based On Context-aware Patterns

A technology for designing layouts and contexts, applied in computing, special data processing applications, instruments, etc., and can solve problems such as the need for manpower

Inactive Publication Date: 2014-08-06
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, once hotspots are identified through pattern matching, manpower is still required to correct the layout

Method used

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  • Automated Design Layout Pattern Correction Based On Context-aware Patterns
  • Automated Design Layout Pattern Correction Based On Context-aware Patterns
  • Automated Design Layout Pattern Correction Based On Context-aware Patterns

Examples

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Embodiment Construction

[0080] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of example embodiments. It should be apparent, however, that the exemplary embodiments may be practiced without these specific details or with equivalent arrangements. In other instances, well-known architectures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the exemplary embodiments. Additionally, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and the like in the specification and claims are to be understood as modified in all instances by the term "about" unless otherwise indicated.

[0081] The present disclosure addresses and resolves the problems of error generation encountered with manual correction of layout patterns of currently difficult-to-manufacture semiconductors and coding difficulties encountered with automated rule-b...

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Abstract

A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern, determining a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern, and replacing the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout.

Description

technical field [0001] The present disclosure relates to generating semiconductor design layouts. The present disclosure is particularly applicable to correcting difficult-to-manufacture patterns in drawn semiconductor design layouts. Background technique [0002] Difficult-to-manufacture patterns within a semiconductor design layout include patterns that produce design rule check errors, lithography printability errors, double patterning technology compatibility check errors, design for manufacturability (DFM) rule check errors, and the like. There are generally two existing solutions for solving difficult-to-manufacture patterns: hand-drawn fixes and automated rule-based fixes. [0003] Freehand corrections are manual corrections made by layout designers using computer-aided design (CAD) tools. Guidance on correcting difficult-to-manufacture patterns is provided in the form of error markers with annotations generated by the rule checking engine. The layout designer must...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/398G06F30/00
Inventor 王道宁戴毅路易奇·卡波迪耶西
Owner GLOBALFOUNDRIES INC