A large-scale chip-on-chip interconnection method and routing algorithm for realizing interconnection structure

Abstract

The invention relates to a method for realizing a chip interconnection structure. A cross-domain direct connection method for large-scale on-chip chip interconnection. For the current on-chip network structure, 1) instantiate a local subnet at the peer node position, and add the local computing nodes connected to the local subnet as a local computing domain ; 2) Between the local computing domains in adjacent locations, the routing nodes of the local subnet are directly connected to construct the main network of the network-on-chip structure. The routing algorithm of the cross-domain direct connection large-scale chip-on-chip interconnection structure, for each local computing domain resource in the chip-on-chip interconnection structure, when the data packet is sent from the source address, it is first judged whether its destination address is in the subnet , if so, use the routing algorithm suitable for the subnet to deliver the data packet; if it is not in the subnet, first send the data packet to the router connected to the external network, and then read the main network address in the destination address in the router, According to the routing algorithm of the main network, the data packet is sent to the subnet corresponding to the destination address; then according to the destination address of the subnet in the data packet, the data packet is sent to the destination address through the routing algorithm of the subnet.

Description

Technical field [0001] The present invention relates to a chip interconnection structure, in particular to a large-scale chip on-chip interconnection structure based on the idea of ​​cross-domain direct connection and a routing algorithm for realizing the structure. Background technique [0002] A typical system-on-chip design often uses two communication strategies, on-chip bus and on-chip network. The main advantages of the on-chip bus are high flexibility, scalability, and low design cost. Generally, the time delay is shorter when the bandwidth requirement is lower; the disadvantage is that the long communication line brings certain energy consumption and limits the system clock rate. When there are more than two modules in the communication structure, scalability is reduced. [0003] The main advantage of the network-on-chip technology is that it can support concurrent communication between hardware modules, is more scalable, and can be used to support greater bandwidth. The ...

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Problems solved by technology

[0006] A cross-domain direct connection method for large-scale on-chip chip interconnection. In the design of chip-on-chip network structure with network interconnection structure, all nodes in the current on-chip network structure are peer-to-peer connected together, which cannot adapt to node localization calculation and data localization. To solve the problem of actual demand for storage, take the following steps:

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