A method of leakage failure analysis of flash memory chips

Abstract

The application discloses a method for failure analysis of leakage between bit lines of a flash memory chip, which relates to the field of chip failure analysis. By adopting a non-destructive analysis process, the FIB segmentation process and the nano-scale probe measurement process are combined, and the method is completely non-destructive. In the case of all materials in the front-end process, the failed plug can be directly located, and it can detect the bridge at different positions of the plug (such as the bridge at the top, middle or any other position of the plug), and can obtain better TEM samples, so as to facilitate the accurate observation of subsequent TEM, that is, while effectively improving the reliability of failure analysis, it can also greatly reduce the time and process costs spent on failure analysis.

Description

technical field [0001] The invention relates to the field of chip failure analysis, in particular to a method for failure analysis of leakage between bit lines of a flash memory chip. Background technique [0002] In various types of traditional flash memory chips (such as mirror bit (Mirror Bit) type flash memory chips or floating gate (Floating Gate) type flash memory chips, etc.), the smallest storage unit is based on a single MOS field effect transistor, and in a physical area In the block, the drain tungsten plugs (Plug) of all column-oriented MOS field effect transistors are connected together by using the bottom metal layer (M1) to form a bit line (Bit Line, BL for short). [0003] Among them, for floating gate (Floating Gate) type flash memory chips, one bottom metal layer (M1) is connected with up to 512 drain tungsten plugs (Plugs) of MOS field effect transistors, and any two plugs in the physical block When the drain tungsten plug (Plug) of adjacent MOS field eff...

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Problems solved by technology

[0007] Similarly, for the situation of tungsten plug bridging caused by insufficient process capability or voids caused by defects, especially when the generated voids are very small and / or only bridges caused by Ti / TiN diffusion, the contrast of SEM observation is very weak , and it is very easy to miss the failure address of the Bridge, which makes it impossible to obtain the abnormal result of the failure analysis (NAF, that is, no abnormality is found); at the same time, the RIE processing itself has a bombardment nature, which may remove the Ti / TiN of the filamentary Bridge, directly lead to the follow-up result as NAF

[0008] In short, the current analysis methods for suspected leakage failure samples of flash memory chips are all destructive analysis, that is, they will cause certain damage to the ILD of the sample during the analysis process, thereby greatly reducing the reliability of failure analysis, and Time and process costs are high

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