Shift register unit, shift register and display device

Abstract

The invention discloses a shift register unit, a shift register and a display device. The shift register unit includes: a voltage boosting module, which is used to , output the first level signal to the signal output module; the signal output module is used to output the gate drive signal under the control of the first clock signal according to the first level signal; the reset module is used to reset the signal Under the control of the control signal output module reset; the pull-down module is used to pull down the output level of the signal output module under the control of the second clock signal. The invention can reduce the power consumption of the integrated circuit and avoid the problem of abnormal waveform caused by the attenuation of the reset signal.

Description

technical field [0001] The invention relates to the field of display technology, in particular to a shift register unit, a shift register and a display device. Background technique [0002] At present, the shift register can integrate the gate (Gate) switch circuit on the array substrate, remove the circuit of the gate drive integrated circuit, and use the shift register to integrate the array substrate. The display composed of the array substrate can save materials and Process steps are reduced, and screen size and product cost are reduced. [0003] The above-mentioned shift register has a plurality of shift register units, and each shift register unit has input terminals such as a first clock signal, a second clock signal and a low voltage signal, and each shift register unit also has an input terminal (Input ), the output terminal (Output) and the reset signal (Reset). However, the output of each stage of the shift register unit in the above shift register is used as th...

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Problems solved by technology

However, the output of each stage of the shift register unit in the above shift register is used as the reset signal of the previous row of shift register units, so as the shift registers are cascaded, there will be a problem that the waveform of the reset signal is abnormal; and , since the first clock signal or the second clock signal and the output terminal are kept in a conduction state during the high level period, the power consumption of the integrated circuit cannot be reduced

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