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Coupled structure for inductor component

A coupling structure and device technology, applied in the direction of logic circuit connection/interface layout, etc., can solve the problems of consuming the total power consumption of integrated circuits, increasing power consumption of clock trees, and affecting performance, etc.

Active Publication Date: 2016-02-03
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As the frequency of the clock signal increases, the power consumed to drive the clock tree also increases
Furthermore, the clock buffers at each stage of the clock tree typically draw large currents from the power grid, causing a voltage drop in the power supply voltage that affects the performance of nearby components
In some applications, the clock tree consumes 20% to 40% of the total power consumption of the integrated circuit

Method used

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  • Coupled structure for inductor component
  • Coupled structure for inductor component
  • Coupled structure for inductor component

Examples

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Embodiment Construction

[0044] The following presents one or more different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to limit the invention. In accordance with the standard practice in the industry, various features in the drawings are not drawn to scale and are used for illustration purposes only.

[0045] In some embodiments, instead of using a clock tree, two or more oscillators configured to generate an output oscillating signal having a predetermined frequency are used to distribute the clock signal to multiple clock components in the integrated circuit. Also, one or more synchronization mechanisms are implemented to minimize frequency or phase differences in oscillating signals generated by the two or more oscillators. In some embodiments, the one or more synchronization mechanisms include magnetic...

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PUM

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Abstract

The present invention provides a circuit, comprising a coupled structure and a first inductor component. The couple structure comprises two or more than two conducting loops or a set of conducting paths electrically connected with the two or more than two conducting loops. The first inductor component is coupled with a first conducting loop of the two or more than two conducting loops. The present invention further provides a method for forming the circuit.

Description

[0001] Cross References to Related Applications [0002] This application is a continuation-in-part of US Provisional Patent Application No. 14 / 075,021, filed October 8, 2013, the entire contents of which are hereby incorporated by reference. technical field [0003] The present invention relates generally to integrated circuits, and more particularly to clock circuits. Background technique [0004] In integrated circuits, clock trees are often used to distribute a common clock signal to multiple components to synchronize the operations of the multiple components. Differences in the arrival times of clock signals of two or more clocked components of an integrated circuit can lead to errors in the operation of the integrated circuit. In some applications, clock trees used to distribute common clock signals include structures such as H-tree meshes or balanced buffer trees. In many cases, the minimization of mismatches in the arrival times of the distributed clock signals is ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/0175
Inventor 陈焕能周淳朴
Owner TAIWAN SEMICON MFG CO LTD