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A Grid Sorting Implementation Method in Semiconductor Process Simulation

A process simulation, semiconductor technology, applied in the direction of instruments, computing, electrical digital data processing, etc., can solve the problems of following others, unable to add semiconductor physical characteristic parameters to the model, expensive and other problems

Active Publication Date: 2019-10-01
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, due to the high price of foreign software and the embargo of some advanced modules to China, the entire source code is invisible to users, unable to understand its entire calculation process, and unable to add the latest semiconductor physical characteristic parameters into the model, so that we The design and production of the company will always follow behind others

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  • A Grid Sorting Implementation Method in Semiconductor Process Simulation
  • A Grid Sorting Implementation Method in Semiconductor Process Simulation
  • A Grid Sorting Implementation Method in Semiconductor Process Simulation

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Embodiment Construction

[0021] In order to make the technical means, creative features, goals and practical effects realized by the present invention easy to understand, the present invention will be further explained below in conjunction with illustrations and specific embodiments:

[0022] In this implementation example, the specific simulation process is as follows:

[0023] 1. According to the input command parameters, the finite element mesh is divided and labeled for the simulation area. The larger the simulation area, the more grids after division. The subsequent numerical solution needs to discretize the nonlinear partial differential equation into a linear equation on the divided grid, so the quality of the topology between the grids is directly related to whether the numerical solution converges and the speed of the convergence. For this, the present invention adopts two kinds of grid labeling methods: bottom-up natural sorting method (such as figure 2 ) and the matrix bandwidth minimiza...

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Abstract

The invention discloses a grid sorting realization method in semiconductor process simulation, which belongs to the field of numerical models. This method first provides two labeling methods in grid generation: bottom-up natural labeling method or discrete matrix bandwidth minimum method; after the grid division is completed, the read process simulation commands are stored in the linear table; By obtaining the process step commands in the linear table, the numerical solution is carried out, and the variable time step method is adopted in the numerical solution process, so that the running solution speed is greatly improved under the condition of ensuring accuracy; finally, the results after the numerical solution can be displayed in the VisIt software View the effect of process technology simulation. The method can not only simulate smaller devices, but also larger devices, and can be comparable to commercial software in simulation speed, and the obtained results are also consistent with commercial software, so the method used in the present invention can be used for Semiconductor process simulation, and it is expected to replace foreign commercial software.

Description

technical field [0001] The invention relates to the field of numerical models, in particular to a grid sorting realization method in semiconductor process simulation. Background technique [0002] At present, the electronic information industry with semiconductor technology as the core has surpassed the traditional technology represented by automobiles and petroleum. With the continuous improvement of circuit integration on silicon wafers and the continuous increase of production processes, often an ordinary integrated circuit, a high-performance device manufacturing, the entire process may include dozens of processes, involving hundreds or even hundreds of processes. Thousands of process parameters. The traditional trial-and-error method has the problems of long cycle and high cost. On the computer, all key process steps can be simulated, which greatly shortens the design time. Therefore, computer-aided design of integrated circuits has become an indispensable and importan...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 谭巍李建清
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA