Method for reducing critical voltage, non-volatile memory and erase operation method thereof

Abstract

The invention relates to a method for reducing critical voltage of a memory, an erase operation method of a non-volatile memory and the non-volatile memory by the method capable of improving critical voltage erase state accuracy of the non-volatile memory. According to the method, at least a memory cell is selected from multiple memory cells of the non-volatile memory according to a first voltage and a second voltage, wherein the first voltage is less than the second voltage; the first voltage is greater than or equal to voltage level of the non-volatile memory in the erase state; and the second voltage is less than or equal to read voltage level of the non-volatile memory. The at least one selected memory cell undergoes a reformed erase operation so as to erase charge of the selected memory cell and reduce critical voltage of the at least one selected memory cell.

Description

technical field [0001] The present invention relates to a method for operating a non-volatile memory and a non-volatile memory, in particular to a method for reducing the critical voltage of the memory, a method for improving the correctness of the memory cell erasing state of the non-volatile memory, and non-volatile memory. Background technique [0002] Non-volatile memory, such as flash memory, includes stacked gates composed of floating gates and control gates. A dielectric layer is placed between the floating gate and the control gate, and a tunnel oxide layer is placed between the floating gate and the substrate. The floating gate is located between the substrate and the control gate and is in a "floating" state (ie, not electrically connected to any circuitry). The control gate is electrically connected to the word line (Word line). The floating gate is used to store charges, and the control gate is used to control data writing / reading operations. A memory cell wi...

AI Technical Summary

Problems solved by technology

However, in the process of erasing, there is always a certain proportion of tail bits (Tail Bits) or stubborn bits (Stubborn Bits) in the entire array, block, or entire group of memory cells, which cannot be erased under certain conditions. After the erase pulse the program confirms the operation by erasing the

This will cause a time delay for the entire erase operation

[0007] The above-mentioned situation that the erase threshold voltage of the memory cell changes with time due to the effect of disturbance, charge accumulation, or other influences will produce many high-boundary (High Boundary) memory cells with a low critical state (LVT). The increase in the number reduces the reliability of memory components

The tail bit or stubborn bit memory cell will also cause a delay in the entire erasing operation time.

And when the memory cells of flash memory are continuously scaled down, or under multi-bit operation, the problem will be more obvious

[0008] It can be seen that the above-mentioned existing non-volatile memory erasing operation method and non-volatile memory obviously still have inconvenience and defects in method, product structure and use, and need to be further improved urgently

In order to solve the above-mentioned existing problems, relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time, and there is no suitable method and structure for general methods and products to solve the above-mentioned problems. This is obviously a problem that relevant industry players are eager to solve

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