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A method and device for improving ram access efficiency

An access efficiency, random access memory technology, applied in memory systems, instruments, input/output to record carriers, etc., can solve the problem of reducing RAM access efficiency, wasting RAM cache space, and fragmenting messages with fewer valid bytes. And other issues

Active Publication Date: 2019-05-31
SANECHIPS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] It can be seen that when the existing fragmented message access system performs read and write operations, since the message needs to be divided into fixed-length fragmented messages, when a piece of fragmented message contains valid characters When the section is relatively small, it will cause some cache chips to permanently store fragmented messages with relatively few valid bytes, which wastes a large RAM cache space and reduces the access efficiency of RAM.

Method used

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  • A method and device for improving ram access efficiency
  • A method and device for improving ram access efficiency
  • A method and device for improving ram access efficiency

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Embodiment Construction

[0020] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention.

[0021] figure 1 A schematic flowchart of a method for improving RAM access efficiency provided by an embodiment of the present invention, the method includes:

[0022] S101: Obtain the second random sequence according to the preset first random sequence and the corresponding relationship between the elements of the first random sequence and the second random sequence; wherein, the number of elements of the first random sequence is equal to the number of the second random sequence Each element of the first random sequence is different from each other and corresponds to a different second random sequence, and the number of elements of the first random sequence is at least two;

[0023] It should be noted that since the number of elements of the first random sequence is the same...

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Abstract

A method for improving RAM access efficiency. The method comprises: obtaining a second random sequence according to a pre-set first random sequence and a correlation between elements of the first random sequence and the second random sequence (S101); obtaining an RAM according to the obtained second random sequence and a correlation between elements of the second random sequence and the RAM (S102); and performing a write / read operation on a packet fragment in the RAM (S103). Also provided at the same time are a device for improving RAM access efficiency and a computer storage medium.

Description

technical field [0001] The present invention relates to the field of mobile terminals, in particular to a method and device for improving random access memory (random access memory, RAM) access efficiency. Background technique [0002] With the continuous growth of network capacity and services, the requirements for the capacity and bandwidth of message buffering during message processing are getting higher and higher. Existing fragmented packet access systems use multiple cache chips, such as RAM, to access packets. Since the processing of each message is through the process of writing-processing-reading, that is, each message is written once and read once, in order to balance the bandwidth of each cache chip, the same message will be fragmented Write to a different cache chip. [0003] However, the cache chip has a length requirement for each access message. For example, the read / write command sent each time by Double Data Rate Synchronous Dynamic Random Access Memory (D...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F3/06
CPCG06F12/00
Inventor 肖洁徐金林廖智勇刘衡祁
Owner SANECHIPS TECH CO LTD