High resolution decoder digital display mixed format bitstream self-adapting processing system and method

Abstract

The invention discloses a high-definition decoder digital display mixed format bitstream self-adapting processing system and method. The high-definition decoder digital display mixed format bitstream self-adapting processing system comprises a decoder, a DDR2 controller, a motion vector up conversion module, a display control module and an output playback module; wherein the decoder is used for reconstructing and decoding the mixed format image to obtain the mixed bitstream; the DDR2 controller is used for the protocol control of the DDR2 physical layer protocol PHY circuit, and used for pre-storing the decoded mixed bitstream to the DDR2 / SDRAM off chip physical memory to realize the data read and write to the DDR2 / SDRAM off chip physical memory; the motion vector up conversion module comprises a direct memory access unit, a high definition motion vector up conversion queue buffer unit and a high definition motion vector up conversion unit; the display control module performs the cyclic redundancy check of chrominance / luminance pixel components; and the output playback module is used for outputting the image to the off chip interface for display. The invention has the advantages such as the mechanism of the invention does not take advantage of the extra time of the CPU, the bus access width of the mixed pixels is fixed, and the format and order of the access pixels can be configured before de-interleaver.

Description

technical field [0001] The invention relates to the field of circuit technology, in particular to a high-definition decoder digital display mixed-format stream adaptive processing system and method. Background technique [0002] At present, the following services are not provided for high-definition image multimedia decoders: pre-storage after decoding of dense stream sources (AVS / MPEG / H.26X) in mixed image formats, gradual transfer based on on-chip bus, and upstream stream processing The cache interface architecture for the unified deinterleaving operation processing of the mixed code stream, the downstream code stream prepares the output buffer interface for the following image output, and the deinterleaving cache interface can perform adaptive configuration adjustment of the code stream format. [0003] The current high-definition multimedia does not provide a unified and effective interface cache architecture for the decoding of dense stream sources (AVS / MPEG / H.26X) in m...

AI Technical Summary

Problems solved by technology

[0006] But it also has certain shortcomings: the patent only explains the calculation architecture for the reset of error data frames, and does not have the structural integrity of the system for post-decoding processing of all code streams in this application

[0008] But it also has certain shortcomings: this patent is based on a software thread method, which is different from the implementation mechanism of the hardware accelerator in this patent. The hardware accelerator implementation can be used as the physical layer of the system, and it has the advantage of being fast for dense pixel processing. In addition, this patent is based on a two-way decoder, which does not have the multiplexability and adaptability of deinterleaving after decoding a set of code streams in the patent application.

[0010] But it also has certain shortcomings: the patent uses FIFO queue buffer to construct input / output buffer, and does not have the hierarchical cache strategy based on the direct storage access unit DMA joint queue FIFO of the patent of this application. The cache architecture of the patent of this application can process data through the CPU. Handling parameter settings, adaptive descrambling of the mixed code stream after decoding; at the same time, the cache strategy of the patent application is based on the custom bus handshake protocol, which is different from the strategy of the patent based on asynchronous clock switching

[0011] To sum up, there are a series of technical problems in the existing technology, including: the mixed image format dense code stream is decoded and temporarily stored off-chip and then transferred to the chip, and the upstream code stream is adaptively deinterleaved. Time / space interpolation operation Effective data handling hierarchical cache architecture, downlink data flow structure after deinterleaving of downlink code stream to display control playback output display, self-adaptive configuration mechanism for mixed data format deinterleaving, handshake protocol based on custom bus for data handling, etc., are still lacking effective solution

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