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A kind of ldpc code decoder based on parity check matrix applied to flash memory

A technology of LDPC code and check matrix, applied in the field of error correction coding, can solve problems such as high throughput rate and low hardware area, and achieve the effects of improving service life, increasing parallelism, and reducing the average number of reads and writes.

Active Publication Date: 2020-08-11
NANJING UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] Purpose of the invention: the present invention discloses a low hardware area, high throughput LDPC code decoder for the defects of current LDPC code decoders

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  • A kind of ldpc code decoder based on parity check matrix applied to flash memory
  • A kind of ldpc code decoder based on parity check matrix applied to flash memory
  • A kind of ldpc code decoder based on parity check matrix applied to flash memory

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Embodiment Construction

[0036] Below in conjunction with specific embodiment, further illustrate the present invention, should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention, after having read the present invention, those skilled in the art will understand various equivalent forms of the present invention All modifications fall within the scope defined by the appended claims of the present application.

[0037] In order to make the technical method and advantages of this decoder clearer, the parameters of the decoder are now embodied and described in more detail with reference to the accompanying drawings.

[0038] Such as Figure 1a As shown, the parity check matrix of the quasi-cyclic LDPC code can be used with the offset parameter P i，j To represent. As shown in Figure 1b, each offset parameter corresponds to a cyclic right-shift matrix of a z×z identity matrix, and its offset is P i，j , wher...

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Abstract

The invention discloses an LDPC code decoder, belonging to the field of error correction coding in non-volatile memories. According to the characteristic that a decoder required for the error correction coding of an NAND flash memory is high in code rate and throughput rate, a min-sum decoding algorithm grouped by columns is adopted based on a check matrix of an arithmetic quasi-cyclic LDPC code. The LDPC code decoder disclosed by the invention has the following beneficial effects: based on the property of the check matrix of the arithmetic quasi-cyclic LDPC code, the area of the decoder can be reduced by avoiding the use of a barrel shifter; the throughput rate of the decoder can be improved by increasing the dimension of a sub-matrix of the arithmetic quasi-cyclic LDPC code; and the decoder is compatible with the use of 1-bit hard information soft decoding and 2-bit soft information soft decoding, the average read and write times of the flash memory can be reduced, and the service life of the flash memory can be prolonged.

Description

technical field [0001] The invention belongs to the technical field of error correction coding in non-volatile memories, and in particular relates to a low hardware area and high pass rate equivariant quasi-cyclic LDPC code decoder applied in the field of flash memory error correction. Background technique [0002] At present, the key application areas of NAND flash memory have been greatly tilted from desktop to mobile, such as mobile phones, tablets, USB flash drives and solid-state drives. An important development trend of NAND flash memory is the development of TLC (Trinary-Level Cell) technology. The earliest NAND flash memory uses SLC (Single-Level Cell) technology, which stores 1-bit information in each storage unit. With the increasing demand for storage capacity brought about by the development of mobile devices, MLC (Multi-Level Cell) technology emerged as the times require, realizing the function of storing 2-bit information in each storage unit. Currently, the ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/11G11C29/42G06F11/10
CPCG06F11/1012G11C29/42H03M13/1111H03M13/1131
Inventor 沙金邵炜胡光辉刘镜伯闫锋
Owner NANJING UNIV