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LDPC code decoder based on arithmetic check matrix for flash memory

A technology of LDPC code and check matrix, applied in the field of error correction coding, can solve the problems of low hardware area and high throughput rate, and achieve the effects of increasing parallelism, improving service life and reducing the average number of reads and writes.

Active Publication Date: 2017-09-01
NANJING UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] Purpose of the invention: the present invention discloses a low hardware area, high throughput LDPC code decoder for the defects of current LDPC code decoders

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  • LDPC code decoder based on arithmetic check matrix for flash memory
  • LDPC code decoder based on arithmetic check matrix for flash memory
  • LDPC code decoder based on arithmetic check matrix for flash memory

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Embodiment Construction

[0036] In the following, the present invention will be further clarified with reference to specific examples. It should be understood that these examples are only used to illustrate the present invention and not to limit the scope of the present invention. After reading the present invention, those skilled in the art will understand various equivalent forms of the present invention. All the modifications fall within the scope defined by the appended claims of this application.

[0037] In order to make the technical methods and advantages of the decoder clearer, the decoder parameters are now embodied with reference to the accompanying drawings, and the decoder is described in more detail.

[0038] Such as Figure 1a As shown, the check matrix of the quasi-cyclic LDPC code can use the offset parameter P i, j To represent. Such as Figure 1b As shown, each offset parameter corresponds to a z×z cyclic right shift matrix of the identity matrix, and its offset is P i, j , Where z is th...

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Abstract

The invention discloses an LDPC code decoder, belonging to the field of error correction coding in non-volatile memories. According to the characteristic that a decoder required for the error correction coding of an NAND flash memory is high in code rate and throughput rate, a min-sum decoding algorithm grouped by columns is adopted based on a check matrix of an arithmetic quasi-cyclic LDPC code. The LDPC code decoder disclosed by the invention has the following beneficial effects: based on the property of the check matrix of the arithmetic quasi-cyclic LDPC code, the area of the decoder can be reduced by avoiding the use of a barrel shifter; the throughput rate of the decoder can be improved by increasing the dimension of a sub-matrix of the arithmetic quasi-cyclic LDPC code; and the decoder is compatible with the use of 1-bit hard information soft decoding and 2-bit soft information soft decoding, the average read and write times of the flash memory can be reduced, and the service life of the flash memory can be prolonged.

Description

Technical field [0001] The invention belongs to the technical field of error correction coding in non-volatile memory, and particularly relates to a low hardware area and high pass rate equal difference quasi-cyclic LDPC code decoder applied to the field of flash error correction. Background technique [0002] At present, the key application areas of NAND flash memory have greatly tilted from desktop to mobile, such as mobile phones, tablets, USB drives and solid state drives. An important development trend of NAND flash memory is the development of TLC (Trinary-Level Cell) technology. The earliest NAND flash memory used SLC (Single-Level Cell) technology, which stores 1-bit information in each memory cell. With the continuous increase in storage capacity requirements brought about by the development of mobile devices, MLC (Multi-LevelCell) technology has emerged to realize the function of storing 2-bit information in each storage unit. At present, the most widely used TLC tech...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M13/11G11C29/42G06F11/10
CPCH03M13/1111H03M13/1131G06F11/1012G11C29/42
Inventor 沙金邵炜胡光辉刘镜伯闫锋
Owner NANJING UNIV