A dual-time domain dynamic frequency conversion test method
A test method and time domain technology, applied in electronic circuit testing, non-contact circuit testing, single semiconductor device testing, etc., can solve problems such as difficulty in the limit operating frequency of internal circuits, asynchronous clocks, and unknown internal actual frequency.
Active Publication Date: 2019-11-26
SHANGHAI HUALI MICROELECTRONICS CORP
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Problems solved by technology
However, when using BIST mode, there are limitations that the external and internal clocks are not synchronized, and the actual internal frequency is unknown.
It is difficult to accurately obtain the internal operating frequency and detect the limit operating frequency of the internal circuit
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[0018] The specific embodiments of the present invention are given below in conjunction with the accompanying drawings, but the present invention is not limited to the following embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in very simplified form and use imprecise ratios, which are only used for the purpose of conveniently and clearly assisting in describing the embodiments of the present invention.
[0019] Please refer to figure 1 , figure 1 Shown is a flow chart of the dual-time-domain dynamic frequency conversion test method in a preferred embodiment of the present invention. The present invention proposes a dual-time-domain dynamic frequency conversion test method, comprising the following steps:
[0020] Step S100: using a low-speed reference frequency on the ATE as a communication frequency;
[0021] Step S200: setting the PLL circuit inside the ...
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The invention provides a double-time-domain dynamic frequency conversion test method. The method comprises the following steps of using a low speed reference frequency on an ATE and taking the frequency as a frequency used for communication; on the ATE, through a BIST circuit, setting a PLL circuit in a chip, generating and acquiring a high frequency signal; through calculation, acquiring synchronous waiting time of an external clock and an internal high speed clock, and operation frequencies of an internal high speed instruction; after internal and external clock domains are synchronized, detecting a current internal high speed clock domain instruction operation result; and through continuously changing PLL setting in the external clock domain, realizing frequency conversion the an internal high speed time domain till that a maximum limiting frequency is detected. By using the double-time-domain dynamic frequency conversion test method, under frequency conversion operation of a high speed chip, a peripheral low-speed ATE is used to test performance.
Description
technical field [0001] The invention relates to the field of semiconductor integrated circuit testing, and in particular to a dual-time domain dynamic frequency conversion testing method. Background technique [0002] Semiconductor automated test system (ATE) is used to detect the integrity of integrated circuit functions, and is the final process of integrated circuit manufacturing to ensure the quality of integrated circuit manufacturing. The general working principle of the existing semiconductor automated test system (ATE) is to select the address of the memory chip under test, read and write data to the comparator inside the tester through the level signal on the input and output pins, and compare the expected value The test process of obtaining the result of PASS / FAIL with the measured logic value. [0003] Chip speed continues to increase, and ATE cannot achieve high-speed testing due to factors such as equipment limitations and probe card leads. BIST (Built-in Self...
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IPC IPC(8): G01R31/26G01R31/303
CPCG01R31/2601G01R31/2851
Inventor 武建宏
Owner SHANGHAI HUALI MICROELECTRONICS CORP