Unlock instant, AI-driven research and patent intelligence for your innovation.

Modeling method for parasitic resistance between sources and substrate and between drains and substrate in MOS device

A MOS device and parasitic resistance technology, which is applied in the modeling field of parasitic resistance between the source and drain of MOS devices and the substrate, can solve problems such as insufficient information characterization, and achieve the effect of avoiding insufficient characterization

Active Publication Date: 2018-02-09
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT +1
View PDF5 Cites 11 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The technical problem to be solved by the present invention is to provide a modeling method for the parasitic resistance between the source and drain of the MOS device and the substrate. The parasitic resistance introduced between them avoids the problem that the traditional MOS equivalent test structure does not fully represent this part of the information, and based on the layout factor, a scalable model of the parasitic resistance between the source and drain of the MOS device and the substrate is established to apply to different The layout of the case

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Modeling method for parasitic resistance between sources and substrate and between drains and substrate in MOS device
  • Modeling method for parasitic resistance between sources and substrate and between drains and substrate in MOS device
  • Modeling method for parasitic resistance between sources and substrate and between drains and substrate in MOS device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0031] A method for modeling parasitic resistance between source and drain of a MOS device and a substrate provided by the present invention comprises the following steps:

[0032] S01: If figure 2 As shown, the equivalent test structure for extracting the parasitic resistance of the MOS substrate is established, wherein the equivalent test structure includes the source, the drain, and the substrate well located at the periphery of the source and drain in the form of interdigitated fingers. There is no pattern between the two sources and drains, forming an STI region, and its corresponding cross-sectional structure is as follows image 3 shown. Because the MOS device is NMOS, the equivalent test structure uses the opposite implantation, that is, P-type implantation, so as to avoid the influence of parasitic diodes on the equivalent test structure, and the substrate well around the device is an N-well NW.

[0033] In this embodiment, the number ns of source electrodes is equ...

Embodiment 2

[0042] A method for modeling parasitic resistance between source and drain of a MOS device and a substrate provided by the present invention comprises the following steps:

[0043] S01: If Figure 4 As shown, the equivalent test structure for extracting the parasitic resistance of the MOS substrate is established, wherein the equivalent test structure includes the source, the drain, and the substrate well located at the periphery of the source and drain in the form of interdigitated fingers. The gate is between the two source and drain, and the source and drain are respectively connected by the metal layer through the form of interdigitation, as the two poles in the resistance test process of the equivalent test structure, the gate is drawn out, and when testing the resistance of the equivalent test structure, scan The gate voltage biases the device channel in the depletion region, and its corresponding cross-sectional structure is as follows Figure 5 shown. Because the MOS...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a modeling method for parasitic resistance between sources and a substrate and between drains and the substrate in an MOS device. The method comprises the following steps of S01: establishing an equivalent test structure for extracting the parasitic resistance of the MOS substrate, wherein a source quantity ns is equal to a drain quantity nd, the width of each of the sources and the drains is lsd, the distance between two adjacent source and drain is l, and the length of each of the sources and the drains is w; S02: taking a group of w, lsd and ns, changing the size ofl to generate a series of equivalent test structures, and testing resistance values of the corresponding equivalent test structures to determine Rsb, Rdb and Rdsb; S03: transforming layout factors w,lsd and ns, calculating corresponding Rsb, Rdb and Rdsb according to the method in the S02 for each group of w, lsd and ns, and according to different layout factors in the equivalent test structuresand corresponding resistance value change laws, building parasitic resistance models of Rsb, Rdb and Rdsb. According to the modeling method for parasitic resistance between the sources and the substrate and between the drains and the substrate in the MOS device, provided by the invention, the problem of insufficient representation of information by a conventional MOS equivalent test structure is avoided.

Description

technical field [0001] The invention relates to the field of semiconductor device testing and modeling, in particular to a modeling method for the parasitic resistance between the source and drain of a MOS device and a substrate. Background technique [0002] In the field of radio frequency integrated circuits, the substrate resistance of MOS devices determines the output characteristics of the device to a large extent, and its influence cannot be ignored. The substrate resistance of MOS devices is bounded by the active region, which can be divided into two parts, one part is the active region, that is, the substrate part below the source and drain regions of the MOS device and the channel region, and the other part is the substrate lead-out and lead-out The portion of the substrate below the shallow trench isolation (STI) region between the terminal and the active region. For the former, due to the existence of the device channel and the influence of the parasitic diode be...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/367
Inventor 刘林林郭奥王全周伟
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT