A Modeling Method for the Surrounding Parasitic Resistance of MOS Device Substrate
A MOS device and parasitic resistance technology, applied in the fields of instruments, electrical digital data processing, CAD circuit design, etc., can solve the problems affecting the results of circuit design, insufficient accuracy of the substrate resistance model, etc., to avoid insufficient characterization.
Active Publication Date: 2021-03-26
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT +1
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Problems solved by technology
In the modeling process of active radio frequency devices in the prior art, a two-port test structure is used to model and characterize it, but in the two-port test structure, this part is difficult to be accurately defined and characterized, resulting in the substrate resistance model Insufficient precision, which affects the result of circuit design
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[0030] In order to make the purpose, technical solution and advantages of the present invention clearer, the specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings.
[0031] It should be noted that in the following specific embodiments, when describing the embodiments of the present invention in detail, in order to clearly show the structure of the present invention for the convenience of description, the structures in the accompanying drawings are not drawn according to the general scale, and the Partial methods, deformations and simplifications are explained, therefore, it should be avoided to be interpreted as a limitation of the present invention.
[0032] MOS devices are divided into PMOS devices and NMOS devices. The following figures and descriptions take NMOS devices as an example. When the device is PMIOS, the modeling method adopted is similar to that of NMOS devices. Only the ty...
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The invention discloses a modeling method for MOS (Metal Oxide Semiconductor) device substrate peripheral parasitic resistance. The modeling method comprises the following steps that: S01: establishing an annular resistance testing structure corresponding to the MOS device; S02: establishing an end resistance aided testing structure; S03: establishing an end resistance scalable model; and S04: testing the resistance Rtot2 of the annular resistance testing structure, substituting the perimeter of an interior loop and the perimeter of an exterior loop into the end resistance scalable model so asto obtain the resistance of R1 and R2, transforming a layout factor to obtain the value of Rsti under different layout sizes, analyzing a change relationship between the Rsti and the above layout sizes, and establishing the scalable model of the MOS device substrate peripheral parasitic resistance, wherein Rsti is equal to Rtot2-R1-R2. By use of the modeling method, which is provided by the invention, for the MOS device substrate peripheral parasitic resistance, the parasitic resistance introduced into the periphery of the active area of the MOS device can be directly represented, and the scalable model of the MOS device substrate peripheral parasitic resistance obtained by modeling can be suitable for layout distribution ways under different situations.
Description
technical field [0001] The invention relates to the field of testing and modeling of semiconductor integrated circuits, in particular to a modeling method for the peripheral parasitic resistance of a MOS device substrate. Background technique [0002] In the field of radio frequency integrated circuits, the substrate resistance of MOS devices determines the output characteristics of the device to a large extent, and its influence cannot be ignored in the design of radio frequency integrated circuits. The substrate resistance of the MOS device is bounded by the active area of the device, which can be divided into two parts, one part is the active area, that is, the substrate part below the source and drain areas of the MOS device and the channel area, and the other part is the periphery of the active area of the device. , that is, the substrate lead-out and the substrate portion below the STI (Shallow Trench Isolation) region between the lead-out and the active region. ...
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IPC IPC(8): G06F30/392G06F30/398
CPCG06F30/367G06F30/39G06F30/392
Inventor 刘林林王全郭奥周伟
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT