High-linearity and low-voltage phase interpolating circuit

Abstract

The invention provides a high-linearity and low-voltage phase interpolating circuit. The high-linearity and low-voltage phase interpolating circuit comprises a state machine, a biasing generation unit, a current-steering digital to analog converter, a voltage-current conversion module, a main multiplexer, a secondary current-steering digital to analog converter, a secondary voltage-current conversion module, a secondary multiplexer and a multiplier. The state machine is used for outputting a control code for controlling the current-steering digital to analog converter and the secondary current-steering digital to analog converter to output differential control current; the biasing generation unit is used for providing biasing current to the current-steering digital to analog converter, thesecondary current-steering digital to analog converter and the multiplier; the voltage-current conversion module and the secondary voltage-current conversion module are used for converting the differential control current to control voltage; the main multiplexer and the secondary multiplexer are controlled by the control code respectively and the control voltage is selected; the multiplier is used for outputting a phase interpolating circuit clock signal according to the control voltage and a clock signal output by a phase-locked loop. According to the high-linearity and low-voltage phase interpolating circuit provided by the invention, the linearity of the phase interpolating circuit can be improved and the non-linearity introduced by high-order harmonic waves is eliminated.

Description

technical field [0001] The invention relates to a serializer and a deserializer, in particular to a phase interpolation circuit in recovering clock data at the receiving end of the serializer and deserializer. Background technique [0002] In serial signal communication, with the continuous improvement of the transmission signal rate, higher design requirements are put forward for the clock and data recovery (CDR) circuit of the receiving end of SERDES (SERializer / DESerializer; serializer and deserializer) . Among them, a dual-loop (Dual Loop) structure clock data recovery (CDR) circuit combining a multi-phase clock output phase-locked loop (Phase Locked Loop, PLL) and a phase interpolator circuit (Phase Interpolator, PI) is more and more used. . [0003] Among them, the design principle of the phase interpolation circuit (PI) is based on the fact that any component whose phase is between the quadrature signals can be approximately represented by a linear combination of th...

AI Technical Summary

Problems solved by technology

[0011] In order to solve the deficiencies in the prior art, the object of the present invention is to provide a high linearity low voltage applied to SERDES receiver clock data recovery which solves the linearity and low power supply voltage problems in the phase interpolation circuit (PI) phase interpolation circuit

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