Method and device of processing atomic writing commands
An atomic write and subcommand technology, applied in the storage field, can solve the problem of not providing atomic write commands for solid-state storage devices
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Embodiment 1
[0092] Figure 5A and Figure 5B is a schematic diagram of an atomic write command and a state change diagram of a corresponding cache unit according to an embodiment of the present disclosure. For the purpose of clear description, the range of the logical address corresponding to the cache unit (that is, the logical address indicated by the metadata of the cache unit) is aligned by 4KB (the starting address is located at an integer multiple address of 4KB, for example, 0, 4KB , 8KB), and the size of the logical address space corresponding to the cache unit is 4KB. For example, the atomic write command 510 indicates to write data into the logical address space 1KB-10KB.
[0093] The atomic write command 510 is divided into multiple subcommands according to the logical address range of the cache unit, and the logical address range accessed by each subcommand does not exceed the logical address range of one cache unit. A cache unit is allocated for the subcommand according to...
Embodiment 2
[0101] Figure 6A and 6B is a schematic diagram of an atomic write command and a state change diagram of a corresponding cache unit according to another embodiment of the present disclosure. As an exemplary embodiment, the write command 610 writes data into a 1KB space in the logical address range 0-1KB, a 4KB space in the logical address range 4KB-7KB, and a 1KB space in the logical address range 10KB-11KB.
[0102] see Figure 6A , split the atomic write command 610 into subcommands L4 / L5 / L6, wherein the subcommand L4 writes data to the space of the logical address range 0-1KB, and the subcommand L5 writes data to the space of the logical address range 4KB-7KB, And the subcommand L6 writes data to the logical address 10KB-11KB space.
[0103] By way of example, there are cache units 612, 614, and 616, wherein the logical address range of the cache unit 612 is 0-3KB, and is in an "occupied" state, but no data is stored in the logical address range 0-1KB; cache The logical...
Embodiment 3
[0109] Figures 7A-7B It is a schematic diagram of an atomic write command and a state change diagram of a corresponding cache unit according to yet another embodiment of the present disclosure. Such as Figure 7A As shown, in order to process the atomic write command 710, it is divided into three subcommands (L7 / L8 / L9) according to the accessed logical address. By way of example, by querying the cache unit, if it is found that the subcommand L7 / L8 / L9 does not hit any cache unit, then allocate a cache unit for the subcommand L7 / L8 / L9 (712 / 714 / 716). Cache units can be allocated according to cache mapping methods such as direct mapping, multi-way set associative or full associative, and cache units can also be allocated from the cache unit pool. As an exemplary implementation, see Figure 7B , the obtained cache unit 712 is in the "idle" state, while the cache unit 714 / 716 is in the "occupied" state, such as Figure 7B as shown in "Status 71".
[0110] Since the atomic writ...
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