Method and apparatus for processing atomic write commands
An atomic write and sub-command technology, applied in the storage field, can solve the problem of not providing atomic write commands for solid-state storage devices
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Embodiment 1
[0092] Figure 5A and Figure 5B is a schematic diagram of an atomic write command and a state transition diagram of a corresponding cache unit according to an embodiment of the present disclosure. For the purpose of clear description, the logical address range corresponding to the cache unit (ie, the logical address indicated by the metadata of the cache unit) is aligned according to 4KB (its starting address is located at an integer multiple of 4KB, for example, 0, 4KB). , 8KB), the size of the logical address space corresponding to the cache unit is 4KB. For example, atomic write command 510 instructs to write data to the logical address space 1KB-10KB.
[0093] The atomic write command 510 is divided into multiple subcommands according to the logical address range of the cache unit, and the logical address range accessed by each subcommand does not exceed the logical address range of one cache unit. Subcommands are allocated buffer locations according to the logical add...
Embodiment 2
[0101] Figure 6A and 6B is a schematic diagram of an atomic write command and a state change diagram of a corresponding cache unit according to another embodiment of the present disclosure. As an example implementation, the write command 610 writes data to a 1KB space in the logical address range 0-1KB, a 4KB space in the logical address range 4KB-7KB, and a 1KB space in the logical address range 10KB-11KB.
[0102] see Figure 6A , split the atomic write command 610 into subcommands L4 / L5 / L6, wherein subcommand L4 writes data to the space of logical address range 0-1KB, and subcommand L5 writes data to the space of logical address range 4KB-7KB, And subcommand L6 writes data to the space of logical address 10KB-11KB.
[0103] By way of example, there are cache units 612, 614, and 616, wherein cache unit 612 has a logical address range of 0-3KB and is in an "occupied" state, but no data is stored in the logical address range 0-1KB; the cache The logical address range of t...
Embodiment 3
[0109] Figures 7A-7B It is a schematic diagram of an atomic write command and a state change diagram of a corresponding cache unit according to yet another embodiment of the present disclosure. like Figure 7A As shown, to process the atomic write command 710, it is split into 3 subcommands (L7 / L8 / L9) by the logical address accessed. By way of example, by querying the cache unit, it is found that the subcommand L7 / L8 / L9 does not hit any cache unit, then the subcommand L7 / L8 / L9 is allocated a cache unit (712 / 714 / 716), for example. Cache units can be allocated according to a cache mapping method such as direct mapping, multi-way set associative or fully associative, and can also be allocated from a cache unit pool. As an example implementation, see Figure 7B , the obtained cache unit 712 is in the "idle" state, while the cache units 714 / 716 are in the "occupied" state, such as Figure 7B shown in "State 71".
[0110] Since the atomic write command 710 misses the cache uni...
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