Clock Duty Cycle Adjustment Circuit
A technology for adjusting the circuit and duty cycle, applied in pulse shaping and other directions, can solve the problem of reducing the data processing capacity of the system, and achieve the effect of flexible circuit structure
Active Publication Date: 2022-03-08
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Problems solved by technology
Generally, 50% duty cycle is the most favorable for data processing, which is the guarantee for stable operation of the system; especially for systems that use rising and falling edges for data processing at the same time, a clock signal with a 50% duty cycle is required, otherwise it will Will reduce the data processing capacity of the system
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[0015] see figure 1 As shown, the clock duty ratio adjustment circuit in the following embodiments includes: a duty ratio adjustment circuit, an analog voltage comparator, a frequency division circuit by two, a control logic circuit and a duty ratio-voltage conversion circuit.
[0016] The duty cycle adjustment circuit adjusts the input clock signal CKIN to be adjusted to generate an adjusted clock signal CKT.
[0017] The divide-by-two circuit generates the adjusted clock signal CKT into a clock with a 50% duty cycle as the reference clock signal CKR.
[0018] The duty ratio-voltage conversion circuit converts the adjusted clock signal CKT to generate an integral voltage signal VCT of the clock duty ratio to be adjusted; converts the reference clock signal CKR to generate the integrated voltage signal VCR of the reference clock duty ratio .
[0019] The analog voltage comparator compares the input duty cycle integrated voltage signal VCT of the clock to be adjusted with the...
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The invention discloses a clock duty ratio adjustment circuit. The duty ratio adjustment circuit adjusts the input clock CKIN to be adjusted to generate an adjusted clock CKT; the two frequency division circuit generates the clock signal CKIN to be adjusted. Become a clock with a 50% duty cycle as the reference clock CKR; the duty cycle-voltage conversion circuit converts the adjusted clock CKT to generate the integrated voltage VCT of the clock duty cycle to be adjusted; converts the reference clock CKR to generate The reference clock duty ratio integrates the voltage VCR; the analog voltage comparator compares the input voltage VCT and VCR, and outputs the comparison result CMPO; the control logic circuit generates an N-bit duty ratio according to the comparison result CMPO to adjust the switching value and control The electronic switch in the duty cycle adjustment circuit achieves the adjustment target. The invention can automatically adjust the duty ratio of the clock to 50%.
Description
technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a clock duty ratio adjustment circuit. Background technique [0002] Clock duty cycle is a very important specification. Generally, 50% duty cycle is the most favorable for data processing, which is the guarantee of stable system operation; especially for systems that use rising and falling edges for data processing at the same time, a clock signal with a 50% duty cycle is required, otherwise it will It will reduce the data processing capacity of the system. Contents of the invention [0003] The technical problem to be solved by the present invention is to provide a clock duty ratio adjustment circuit, which can automatically adjust the clock duty ratio to 50%. [0004] In order to solve the above-mentioned technical problems, the clock duty ratio adjustment circuit of the present invention includes: a duty ratio adjustment circuit, an analog voltage comparat...
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IPC IPC(8): H03K5/04
CPCH03K5/04
Inventor 赵锋邵博闻
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP