Method and device for clock synchronization

A clock synchronization and clock technology, applied in the field of communication, can solve the problem of inaccurate clock synchronization of multi-lane interfaces

Active Publication Date: 2020-12-11
SHENZHEN ZHONGXING SOFTWARE CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] One aspect of the present application provides a method and device for clock synchronization, which can solve the problem of inaccurate clock synchronization of multi-lane interfaces

Method used

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  • Method and device for clock synchronization
  • Method and device for clock synchronization
  • Method and device for clock synchronization

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0090] Embodiment 1. A clock synchronization method, such as figure 1 As shown, including steps S110-S120:

[0091] S110. The synchronization terminal device generates a time stamp according to the receiving and sending time of the aligned code block on the predetermined channel;

[0092] S120. The synchronization terminal device and the synchronized terminal device receive and send time information messages, and determine the time between the synchronized terminal device and the synchronized terminal device through the time stamp of the aligned code block that matches the receiving and sending time information message deviation;

[0093] S130. The synchronization end device adjusts the system clock according to the determined time offset.

[0094] Wherein, the synchronizing terminal device may refer to a device to be synchronized with the synchronized terminal device, and the synchronized terminal device may refer to a device with a clock as a reference standard for synchro...

Embodiment 2

[0120] Embodiment 2, a method for clock synchronization, applied to equipment including multiple time counting systems, the multiple time counting systems are divided into a master time counting system and a slave time counting system; the method is as follows figure 2 As shown, including steps S210-S220:

[0121] S210. Obtain a common divisor from the clock frequency of the main time counting system according to the master time counting system, and create a common divisor clock with the common divisor as the clock frequency;

[0122] S220. Synchronize the common denominator clock with the clock of the master time counting system, and synchronize the clock of the slave time counting system with the common denominator clock.

[0123] In this embodiment, the clock frequency of the time counting system used for timestamping is related to the interface rate, different rate interfaces correspond to time counting systems at different clock frequencies, and each time counting system...

Embodiment 3

[0135] Embodiment 3. A clock synchronization method. In this embodiment, the periodic code block adopts the alignment code block AM, and the clock synchronization process includes the following steps S310-S370:

[0136] Step S310, frequency synchronization.

[0137] Synchronize the frequency of the system clock of the synchronizing end device and the synchronized end device. .

[0138] Step S320, generating a time stamp.

[0139] Detect the alignment code block AM of the specified lane in the sending and receiving direction, record its sending or arrival time, and generate a timestamp.

[0140] The time stamp may be generated by a time counting system corresponding to the aligned code block; wherein, the time counting system corresponding to the aligned code block may include an interface parallel clock (that is, a clock corresponding to the interface parallel data) and a time counter.

[0141] In step S330, the system clock and the interface parallel clock are phase-identi...

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Abstract

Disclosed are a clock synchronization method and device. The clock synchronization method comprises: a synchronizing end device generates a time stamp according to a receiving time and a transmitting time of a periodic code block over a predetermined channel; the synchronizing end device transmits a time information message to and receives a time information message from a synchronized end device, and determines a time difference with the synchronized end device according to time stamps of periodic code blocks matching the transmitting and receiving of time information messages; and the synchronizing end device adjusts the system clock according to the determined time difference. Embodiments of the present invention further provide a computer storage medium.

Description

technical field [0001] The present invention relates to the communication field, in particular to a clock synchronization method and device. Background technique [0002] The multi-lane (channel) interface pcs (Physical Code Sublayer, physical coding sublayer) and pma (Physical Media Access, physical media access layer) are partly due to the distribution and merging of code blocks, the conversion of data bit width and the conversion of clock domain, etc. , fifo (First Input First Output, first-in-first-out), gearbox (gearbox), etc. are usually used in implementation, and the processing delay is not easy to determine. If the header of the time information packet is still used as the reference point, and the time stamp is stamped at the mac (MediaAccess Control, Media Access Control) layer, the time jitter will be relatively large and the accuracy will be relatively poor. [0003] At present, the method of increasing the clock frequency of the time counter is generally used t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04J3/06H04L7/00
CPCH04J3/065H04L7/0016H04J3/06H04L7/00H04W56/00
Inventor 李霞何力游俊马昊昊
Owner SHENZHEN ZHONGXING SOFTWARE CO LTD
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