Clock synchronization method and device

A clock synchronization and clock technology, applied in the field of communication, can solve the problem of inaccurate clock synchronization of multi-lane interfaces

Active Publication Date: 2018-11-23
SHENZHEN ZHONGXING SOFTWARE CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] One aspect of the present application provides a method and device for clock synchroniz

Method used

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  • Clock synchronization method and device
  • Clock synchronization method and device

Examples

Experimental program
Comparison scheme
Effect test

Example Embodiment

[0090] Embodiment 1. A method of clock synchronization, such as figure 1 As shown, including steps S110 to S120:

[0091] S110. The synchronization terminal device generates a time stamp according to the receiving and sending time of the aligned code block on the predetermined channel;

[0092] S120. The synchronization terminal device receives and transmits time information packets between the synchronized terminal device and the synchronized terminal device, and determines the time between the synchronized terminal device and the synchronized terminal device through the time stamp of the alignment code block matching the received and transmitted time information packet. deviation;

[0093] S130. The synchronization terminal device adjusts the system clock according to the determined time deviation.

[0094] Among them, the synchronization end device may refer to a device that is to be synchronized with the synchronized end device, and the synchronized end device may refer to a devic...

Example Embodiment

[0120] Embodiment 2. A method of clock synchronization is applied to a device including multiple time counting systems, the multiple time counting systems are divided into a master time counting system and a slave time counting system; the method is as figure 2 As shown, including steps S210 to S220:

[0121] S210: Obtain a common divisor according to the clock frequency of the master time counting system and the slave time counting system, and create a common divisor clock using the common divisor as the clock frequency;

[0122] S220. Synchronize the common divisor clock with the clock of the master time counting system, and synchronize the clock of the slave time counting system with the common divisor clock.

[0123] In this embodiment, the clock frequency of the time counting system used for time stamping is related to the interface rate. Different rate interfaces correspond to time counting systems at different clock frequencies, and each time counting system uses a common divi...

Example Embodiment

[0135] Embodiment 3. A method for clock synchronization. In this embodiment, the periodic code block adopts the alignment code block AM, and the clock synchronization process includes the following steps S310 to S370:

[0136] Step S310, frequency synchronization.

[0137] Synchronize the frequency of the system clock of the synchronized end device and the synchronized end device. .

[0138] Step S320, the time stamp is generated.

[0139] Detect the alignment code block AM of the specified lane in the sending and receiving direction, record the time of its sending or arrival, and generate a time stamp.

[0140] The time stamp may be generated by a time counting system corresponding to the alignment code block; wherein the time counting system corresponding to the alignment code block may include an interface parallel clock (that is, a clock corresponding to the interface parallel data) and a time counter.

[0141] Step S330, phase discrimination between the system clock and the interfa...

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Abstract

The application provides a clock synchronization method and device. The clock synchronization method includes the following steps that: synchronization end equipment generates a timestamp according tothe time of receiving and sending a periodic code block on a predetermined channel; the synchronization end equipment performs time information message receiving and transmission with synchronized end equipment, and determines a time deviation with the synchronized end equipment according to the timestamp of the periodic code block matching the received and transmitted time information messages;and the synchronization end equipment adjusts a system clock according to the determined time deviation.

Description

technical field [0001] The present invention relates to the communication field, in particular to a clock synchronization method and device. Background technique [0002] The multi-lane (channel) interface pcs (Physical Code Sublayer, physical coding sublayer) and pma (Physical Media Access, physical media access layer) are partly due to the distribution and merging of code blocks, the conversion of data bit width and the conversion of clock domain, etc. , fifo (First Input First Output, first-in-first-out), gearbox (gearbox), etc. are usually used in implementation, and the processing delay is not easy to determine. If the header of the time information packet is still used as the reference point, and the time stamp is stamped at the mac (MediaAccess Control, Media Access Control) layer, the time jitter will be relatively large and the accuracy will be relatively poor. [0003] At present, the method of increasing the clock frequency of the time counter is generally used t...

Claims

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Application Information

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IPC IPC(8): H04J3/06H04L7/00
CPCH04J3/065H04L7/0016H04J3/06H04L7/00H04W56/00
Inventor 李霞何力游俊马昊昊
Owner SHENZHEN ZHONGXING SOFTWARE CO LTD
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