Interrupt processing function verification system and method
A technology of functional verification and verification system, which is applied in the field of interrupt processing function verification system, can solve the problems of long time, increase of missing errors, poor reusability of verification system, etc., and achieve high efficiency, strong completeness, versatility and reliability Transplantation effect
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Embodiment 1
[0049] An interrupt processing function verification system provided by an embodiment of the present invention is introduced in detail.
[0050] refer to figure 1 , shows a schematic diagram of an interrupt handling function verification system in an embodiment of the present invention. The system includes:
[0051] A sequence generator 101, configured to generate interrupt data, where the interrupt data includes configuration values or interrupt sources of the interrupt processor;
[0052] a driver 102, configured to convert the interrupt data into an interrupt input signal, and send the interrupt input signal to an interrupt processor;
[0053] The interrupt processor 103 is configured to configure the interrupt processor when the received interrupt input signal is a configuration value of the interrupt processor; when the received interrupt input signal is an interrupt source, configure the interrupt The source performs interrupt processing to generate an interrupt res...
Embodiment 2
[0075] refer to image 3 , shows a schematic diagram of an interrupt handling function verification system in an embodiment of the present invention. This embodiment is based on the first embodiment.
[0076] The interrupt responder 1033 is further configured to generate first bus protocol data and send the generated first bus protocol data to the scoreboard 104, wherein the first bus protocol data includes the interrupt controller The channel information of the write address channel and the write data channel;
[0077] The interrupt controller 1031 is further configured to generate second bus protocol data, wherein the second bus protocol data includes channel information of the write address channel and the write data channel;
[0078] A bus protocol monitor 1034, configured to monitor the second bus protocol data generated by the interrupt controller 1031, and send the second bus protocol data to the scoreboard 104;
[0079] The scoreboard 104 is further configured to ve...
Embodiment 3
[0087] A method for verifying an interrupt processing function provided by an embodiment of the present invention is introduced in detail.
[0088] refer to Figure 4 , which shows a flow chart of the steps of a method for verifying an interrupt processing function in an embodiment of the present invention, which is applied to the system for verifying the interrupt processing function described in Embodiment 1 to Embodiment 2, and the method includes:
[0089] Step 201, generate interrupt data, wherein the interrupt data includes configuration values of interrupt processors or interrupt sources.
[0090] In this embodiment, the interrupt data is generated by the sequence generator 101 in the verification system, and the interrupt data includes configuration values write_valid, write_addr, write_data or interrupt source ioint of the interrupt handler. The sequence generator 101 can randomly generate a large number of input stimuli in a short period of time according to the s...
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