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Semiconductor device and method of manufacturing same

A semiconductor and electrical conductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as wafer cracking

Active Publication Date: 2019-02-26
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, wafer cracking and stress issues are challenges in 3DIC

Method used

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  • Semiconductor device and method of manufacturing same
  • Semiconductor device and method of manufacturing same
  • Semiconductor device and method of manufacturing same

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Embodiment Construction

[0015] The following disclosure provides many different embodiments, or examples, of different means for implementing the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of the disclosure. Of course, these are examples only and are not intended to be limiting. For example, descriptions in which a first component is formed over or on a second component may include embodiments in which the first component is formed in direct contact with the second component and may also include embodiments in which additional components may be formed on An embodiment in which the first member and the second member are not in direct contact with each other. In addition, the embodiments of the present disclosure may repeat reference numerals and / or letters in various instances. This repetition is for simplicity and clarity and does not inherently indicate a relationship between the various embodiments and / or configurations di...

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Abstract

The disclosure relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate, electrical conductors and a passivation layer. Each of the electrical conductors includes a first portion through the substrate, and a second portion over the surface of the substrate and connected to the first portion. The passivation layer is over the surface ofthe substrate, wherein the passivation layer partially covers an edge of the second portion of each of the electrical conductors.

Description

technical field [0001] The present disclosure relates to semiconductor devices and methods of manufacturing the same. Background technique [0002] In the packaging of integrated circuits, semiconductor die may be stacked by bonding and may be bonded to other package components such as interposers and package substrates. The resulting package is called a three-dimensional integrated circuit (3DIC). However, wafer cracking and stress issues are challenges in 3DIC. Contents of the invention [0003] One embodiment of the present invention relates to a semiconductor device comprising: a substrate including a first surface; a plurality of first electrical conductors, wherein each of the plurality of first electrical conductors includes a a first portion of the substrate, and a second portion positioned above the first surface of the substrate and connected to the first portion; and a passivation layer positioned above the first surface of the substrate , wherein the passiva...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/488H01L21/48
CPCH01L23/488H01L24/10H01L24/11H01L2224/11013H01L2224/10155H01L24/13H01L2224/10126H01L2224/16238H01L2224/73204H01L2224/97H01L2224/0401H01L2224/13007H01L24/16H01L23/3128H01L2224/16227H01L25/0655H01L2924/15311H01L2924/18161H01L23/49816H01L23/5384H01L23/49894H01L23/49838H01L21/4853H01L23/49827H01L25/16H01L21/563H01L24/81
Inventor 林俊成郑礼辉蔡柏豪
Owner TAIWAN SEMICON MFG CO LTD