Semiconductor device and method for manufacturing same

[0022] Hereinafter, some embodiments will be described in detail with reference to the accompanying drawings to help clearly understand the inventive concept.

[0023] figure 1 A plan view illustrating a semiconductor device according to an exemplary embodiment is shown. figure 2 shows along figure 1 Cross-sectional views taken along lines II', II-II', and II-III' of . image 3 shows showing figure 1 perspective view of the gate structure.

[0024] refer to Figure 1 to Figure 3 , the substrate 100 may be provided thereon with a device isolation layer ST defining an active pattern ACT. The substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate, or may include a silicon substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate. The device isolation layer ST may include, for example, oxide, nitride, or oxynitride. The active patterns ACT may extend in a direction D1 parallel to the top surface of the substrate 100 . In some embodiments, as figure 2 As shown in , the device isolation layer ST may have a top surface that is substantially coplanar with the top surface of the active pattern ACT. In other embodiments, with figure 2 Unlike shown in , the device isolation layer ST may expose side surfaces of upper portions of the active patterns ACT. In this case, the active pattern ACT may include an upper portion (or fin) exposed by the device isolation layer ST.

[0025] The substrate 100 may be provided thereon with the gate structure GS spanning the active pattern ACT. The gate structure GS may extend in the second direction D2 parallel to the top surface of the substrate 100 . The first direction D1 and the second direction D2 may cross each other and be perpendicular to each other. A plurality of gate structures GS may be provided on the substrate 100 . The plurality of gate structures GS may extend across the active pattern ACT and may be spaced apart from each other along the first direction D1.

[0026] The gate structure GS may include a gate electrode GE extending across the active pattern ACT, a capping pattern CAP on the gate electrode GE, a gate dielectric pattern GI between the gate electrode GE and the substrate 100, and a gate electrode GE on the gate electrode GE. Gate spacers GSP on side surfaces. The gate electrode GE may have a linear shape extending in the second direction D2. The gate spacers GSP may be correspondingly disposed on opposite side surfaces of the gate electrode GE, and each of the gate spacers GSP may extend in the second direction D2 along the corresponding side surfaces of the gate electrode GE. The gate dielectric pattern GI may extend in the second direction D2 along the bottom surface of the gate electrode GE, and may extend in the second direction D2 along the side surface of the gate electrode GE between the gate electrode GE and each gate spacer GSP. It extends in the two directions D2. The gate electrode GE may include one or more of conductive metal nitrides (eg, titanium nitride, tantalum nitride, etc.) and metals (eg, aluminum, tungsten, etc.). The gate electrode GE may include metal materials having different work functions from each other. The gate dielectric pattern GI may include at least one high-k dielectric layer. For example, the gate dielectric pattern GI may include one or more of hafnium oxide, hafnium silicate, zirconium oxide, and zirconium silicate. The gate spacer GSP may include nitride (eg, silicon nitride).

[0027] The capping pattern CAP may extend in the second direction D2 along the top surface of the gate electrode GE. The capping pattern CAP may include an upper capping pattern 120 on the gate electrode GE and a lower capping pattern 110 between the gate electrode GE and the upper capping pattern 120 . Each of the lower capping patterns 110 and the upper capping patterns 120 may extend in the second direction D2 along the top surface of the gate electrode GE when viewed in a plan view. The lower capping pattern 110 may separate the upper capping pattern 120 from the gate electrode GE. For example, the upper capping pattern 120 may be spaced apart from the gate electrode GE across the lower capping pattern 110 in the vertical direction. The capping pattern CAP may further include a boundary between the upper capping pattern 120 and the lower capping pattern 110, and the boundary between the upper capping pattern 120 and the lower capping pattern 110 may include oxide.

[0028] The lower capping pattern 110 may include a first portion 110P1 between the gate electrode GE and the upper capping pattern 120 in a horizontal direction and a second portion 110P1 extending from the first portion 110P1 to a corresponding side surface of the upper capping pattern 120 in a vertical direction. Section 110P2. The second portions 110P2 of the lower capping patterns 110 may be correspondingly disposed on opposite side surfaces of the upper capping patterns 120 , and each of the second portions 110P2 may be in the second direction D2 along the corresponding side surfaces of the upper capping patterns 120 up extension. The topmost surface of the lower capping pattern 110 may be the topmost surface of each of the second parts 110P2. In other embodiments, each of the second portions 110P2 of the lower capping pattern 110 may have a shape that tapers in a direction away from the substrate 100 , different from that shown. For example, each of the second portions 110P2 may have a width in the first direction D1, and the width of each of the second portions 110P2 in the first direction D1 may be along a direction away from the substrate 100 (ie, in the vertical direction) decreases. The lower capping pattern 110 may be shaped in a U shape when viewed in cross section. The gate dielectric pattern GI may extend between each of the gate spacers GSP and the gate electrode GE so as to be in contact with the lower capping pattern 110 . For example, the topmost surface of the gate dielectric pattern GI may contact the lower surface of the lower capping pattern 110 at a region under the second portion 110P2.

[0029]It will be understood that when an element is referred to as being "connected" or "coupled" to or "on" another element, it can be directly connected or coupled to the other element, or directly On the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" to, "directly coupled to", or "directly on" another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (eg, "between" versus "directly between," "adjacent" versus "directly adjacent," etc.). However, unless the context dictates otherwise, the terms "contacting" or "in contact with" as used herein mean direct connection (ie, touching).

[0030] The upper capping pattern 120 may cover the topmost surface 110U of the lower capping pattern 110 . For example, the upper capping pattern 120 may cover the topmost surface 110U of each of the second portions 110P2 of the lower capping pattern 110 . The upper capping pattern 120 may be in contact with the topmost surface 110U of the lower capping pattern 110 . The topmost surface 110U of the lower capping pattern 110 may be located at a height lower than that of the top surface 120U of the upper capping pattern 120 with respect to the substrate 100 in the vertical direction. A portion of the upper capping pattern 120 may be interposed between the second portions 110P2 of the lower capping pattern 110 . The portion of the upper capping pattern 120 may fill the space between the second portions 110P2 of the lower capping pattern 110 .

[0031] The upper capping pattern 120 may include a body 120BP and a protrusion 120PP protruding from the body 120BP toward the substrate 100 . The body 120BP may have a first width W1, and the protrusion 120PP may have a second width W2 smaller than the first width W1. The first width W1 may be the maximum width of the body 120BP when measured along the first direction D1, and the second width W2 may be the maximum width of the protrusion 120PP when measured along the first direction D1. exist figure 2 In the example shown in , the width of the body 120BP and the width of the protrusion 120PP may be constant widths in the vertical direction. In some embodiments, when each of the second portions 110P2 of the lower cover pattern 110 has a shape that tapers away from the substrate 100 along the vertical direction, the second portion of the protrusion 120PP is different from that shown. The width W2 may increase in a direction away from the substrate 100 along the vertical direction. The protrusions 120PP of the upper capping patterns 120 may be interposed between the second portions 110P2 of the lower capping patterns 110 , and the bodies 120BP of the upper capping patterns 120 may cover the topmost surface 110U of each of the second portions 110P2 of the lower capping patterns 110 . The main body 120BP of the upper capping pattern 120 may be in contact with the topmost surface 110U of each of the second portions 110P2 of the lower capping pattern 110 . The topmost surface 110U of the lower capping pattern 110 may be located at a height lower than that of the top surface 120U of the body 120BP of the upper capping pattern 120 with respect to the substrate 100 in the vertical direction. Each of the lower capping patterns 110 and the upper capping patterns 120 may include nitride (eg, silicon nitride).

[0032] The source/drain regions SD may be disposed in the active patterns ACT on opposite sides of the gate structures GS. For example, the source/drain regions SD may be formed between adjacent ones of the gate spacers GSP in the active pattern ACT. The active pattern ACT may have a portion under the gate structure GS and overlapping the gate structure GS in the vertical direction, and the portion of the active pattern ACT may serve as a channel region CH. The interlayer dielectric layer 130 may be disposed on the substrate 100 and cover the gate structure GS and the source/drain regions SD. For example, in figure 2 , the interlayer dielectric layer 130 may surround the side surfaces of the gate structure GS and cover the source/drain regions SD. The interlayer dielectric layer 130 may have a top surface 130U substantially coplanar with the top surface 120U of the upper capping pattern 120 (or with the top surface 120U of the body 120BP of the upper capping pattern 120 ). For example, the top surface 130U of the interlayer dielectric layer 130 may be located at the same vertical height as the top surface 120U of the upper capping pattern 120 . The topmost surface 110U of the lower capping pattern 110 (or the topmost surface 110U of each of the second portions 110P2 of the lower capping pattern 110 ) may be located more vertically than the top of the interlayer dielectric layer 130 with respect to the substrate 100 . At a height where the height of the surface 130U is low. The interlayer dielectric layer 130 may include, for example, a silicon oxide layer.

[0033] Contacts 140 may be disposed on opposite sides of the gate structure GS. The contacts 140 may penetrate the interlayer dielectric layer 130 to be electrically connected with the substrate 100 . The contacts 140 may be electrically connected to corresponding source/drain regions SD on opposite sides of the gate structure GS. Contacts 140 may include one or more of doped semiconductors, metals, metal silicides, and conductive metal nitrides.

[0034] The gate structure GS may include a first region R1 and a second region R2, opposite sides of the first region R1 are provided with the contacts 140, and opposite sides of the second region R2 are provided without the contacts 140. At the first region R1 of the gate structure GS, the upper capping pattern 120 may be in contact with the contact 140 . For example, at the first region R1 of the gate structure GS, the body 120BP of the upper capping pattern 120 may be in contact with the contact 140 . At the second region R2 of the gate structure GS, the gate spacers GSP may extend onto corresponding side surfaces of the capping patterns CAP, and the topmost surface of each of the gate spacers GSP may be connected with the interlayer dielectric layer The top surface 130U of 130 is substantially coplanar. In some embodiments, the gate spacer GSP may have a shape that tapers as the gate spacer GSP gets closer to the top surface 130U of the interlayer dielectric layer 130 . Each of the gate spacers GSP may be interposed between the capping pattern CAP and the interlayer dielectric layer 130 and may be in contact with the capping pattern CAP. For example, at the second region R2 of the gate structure GS, each of the second portions 110P2 of the lower capping patterns 110 may be interposed between the protrusions 120PP of the upper capping pattern 120 and each of the gate spacers GSP, Contact with each of the gate spacers GSP at the same time. At the second region R2 of the gate structure GS, the body 120BP of the upper capping pattern 120 may be in contact with the gate spacer GSP.

[0035] The gate structure GS and the source/drain regions SD may constitute a field effect transistor. For example, the gate structure GS and the source/drain regions SD may constitute a P-type field effect transistor. Although not shown, the interlayer dielectric layer 130 may have wirings connected to the contacts 140 disposed thereon. Wiring (not shown) may be electrically connected to the source/drain regions SD through the contacts 140 .

[0036] Figure 4 to Figure 10 shows along figure 1 Cross-sectional views taken along line II', line II-II', and line III-III' of , illustrating a method of fabricating a semiconductor device according to an exemplary embodiment.

[0037] refer to Figure 4 , a device isolation layer ST may be formed on the substrate 100 to define an active pattern ACT. An STI (Shallow Trench Isolation) process may be used to form the device isolation layer ST. The active pattern ACT may be formed to extend in the first direction D1.

[0038] An etch stop layer (not shown) and a sacrificial gate layer (not shown) may be sequentially formed on the substrate 100 . The etch stop layer may include, for example, a silicon oxide layer. The sacrificial gate layer may include a material that is etch selective to the etch stop layer. The sacrificial gate layer may include, for example, polysilicon. The sacrificial gate layer may be patterned to form the sacrificial gate pattern 160 . The sacrificial gate pattern 160 may be formed to extend in the second direction D2 and span the active pattern ACT. The formation of the sacrificial gate pattern 160 may include forming a gate mask pattern 170 on the sacrificial gate layer and etching the sacrificial gate layer by using the gate mask pattern 170 as an etch mask. The gate mask pattern 170 may include, for example, silicon nitride. The etching of the sacrificial gate layer may include performing an etching process that is etch selective to the etch stop layer. After the sacrificial gate pattern 160 is formed, the etch stop layer may be removed from the opposite side of the sacrificial gate pattern 160 so that the etch stop pattern 150 may be formed under the sacrificial gate pattern 160 . The etch stop pattern 150 may extend in the second direction D2 along the bottom surface of the sacrificial gate pattern 160 .

[0039] Gate spacers GSP may be correspondingly formed on side surfaces of the sacrificial gate patterns 160 . The gate spacer GSP may include, for example, silicon nitride. The formation of the gate spacers GSP may include forming a gate spacer layer (not shown) on the substrate 100 on which the sacrificial gate patterns 160 are formed and anisotropically etching the gate spacer layer.

[0040] Source/drain regions SD may be formed in the active patterns ACT on opposite sides of the sacrificial gate pattern 160 . The formation of the source/drain regions SD may include, for example, performing a selective epitaxial growth process to form epitaxial patterns in the active patterns ACT on opposite sides of the sacrificial gate patterns 160 . Alternatively, the formation of the source/drain regions SD may include performing an ion implantation process to form impurity doped regions in the active patterns ACT on opposite sides of the sacrificial gate pattern 160 .

[0041] refer to Figure 5 , an interlayer dielectric layer 130 may be formed on the substrate 100 to cover the sacrificial gate patterns 160 and the source/drain regions SD. The interlayer dielectric layer 130 may include, for example, silicon oxide. The interlayer dielectric layer 130 may be planarized to expose the top surfaces of the sacrificial gate patterns 160 and the top surfaces of the gate spacers GSP. The gate mask pattern 170 may be removed when the interlayer dielectric layer 130 is planarized.

[0042] refer to Image 6 , the sacrificial gate pattern 160 and the etch stop pattern 150 may be removed. Accordingly, gaps 180 may be formed between the gate spacers GSP in the interlayer dielectric layer 130 . For example, a gap 180 may be formed between each pair of gate spacers GSP. The formation of the gap 180 may include etching the sacrificial gate pattern 160 and the etch stop pattern 150 by performing an etch process with etch selectivity to the interlayer dielectric layer 130 and the gate spacer GSP.

[0043] A gate dielectric pattern GI and a gate electrode GE may be formed in the gap 180 . For example, the formation of the gate dielectric pattern GI and the gate electrode GE may include forming a gate dielectric layer (not shown) partially filling the gap 180 on the interlayer dielectric layer 130, forming on the gate dielectric layer The gate electrode layer (not shown) of the gap 180 is completely filled, and the gate dielectric layer and gate electrode layer are planarized until the top surface 130 of the interlayer dielectric layer is exposed. The planarization process may expose the top surfaces of the gate spacers GSP. The gate electrode layer may be etched on the upper portion of the gate electrode layer until the gate electrode layer reaches a desired thickness in the gap 180 to form the gate electrode GE. In addition, the gate dielectric layer may be etched on an upper portion of the gate dielectric layer not covered by the gate electrode GE to form a gate dielectric pattern GI. The gate dielectric pattern GI may be interposed between the gate electrode GE and the substrate 100, and may extend between the gate electrode GE and each of the gate spacers GSP. In some embodiments, the gate dielectric pattern GI may have a topmost surface located at substantially the same level as the top surface of the gate electrode GE with respect to the substrate 100 in the vertical direction. The gate electrode GE and the gate dielectric pattern GI may fill the lower portion of the gap 180 .

[0044] refer to Figure 7 , a lower capping layer 182 may be formed on the interlayer dielectric layer 130 to partially fill the upper portion of the gap 180 . The lower capping layer 182 may be formed to conformally cover the inner surface of the upper portion of the gap 180 , the top surface of the gate electrode GE, and the topmost surface of the gate dielectric pattern GI. The formation of the lower capping layer 182 may include the H 2 The first deposition process is performed in an atmosphere with a relatively low plasma density. For example, the first deposition process may include indirect H 2 Plasma treated or not including H 2 Plasma treatment. The first deposition process may be (or may include) the H 2 An atomic layer deposition process performed in an atmosphere with a relatively low plasma density. The lower capping layer 182 may include, for example, silicon nitride.

[0045] A mask pattern 185 may be formed in the gap 180 to cover a portion of the lower capping layer 182 . The formation of the mask pattern 185 may include forming a mask layer filling the remaining portion of the upper portion of the gap 180 and etching the mask layer until the mask layer reaches a desired thickness in the vertical direction in the upper portion of the gap 180 . The mask pattern 185 may include, for example, a spin-on hard mask (SOH) material (eg, a carbon-containing layer).

[0046] refer to Figure 8 , other parts of the lower capping layer 182 not covered by the mask pattern 185 may be removed to form the lower capping pattern 110 . The lower capping pattern 110 may be interposed between the mask pattern 185 and the gate electrode GE and between the mask pattern 185 and the gate dielectric pattern GI, and may extend between the mask pattern 185 and each gate spacer GSP . The topmost surface 110U of the lower capping pattern 110 may be located at substantially the same level as the top surface of the mask pattern 185 with respect to the substrate 100 in the vertical direction.

[0047] refer to Figure 9 , the mask pattern 185 may be removed. The mask pattern 185 may be removed by performing an ashing process and/or a lift-off process. After removing the mask pattern 185 , an upper capping layer 187 may be formed on the interlayer dielectric layer 130 to fill the remaining portion of the gap 180 . The formation of the upper capping layer 187 may include the H 2 The second deposition process is performed in an atmosphere with a relatively high plasma density. For example, the second deposition process may include direct H 2 Plasma treatment. The second deposition process may be (or may include) the H 2 An atomic layer deposition process performed in an atmosphere with a relatively high plasma density. The upper capping layer 187 may include, for example, silicon nitride. Since in H 2 The plasma density is higher than the H of the atmosphere in which the first deposition process is performed 2 The second deposition process is performed in an atmosphere with a relatively high plasma density, and thus the upper capping layer 187 may have a smaller impurity content than that of the lower capping layer 182 . Therefore, the upper capping layer 187 may be formed to have a higher density than that of the lower capping layer 182 .

[0048] refer to Figure 10 , the upper capping layer 187 may be planarized until the interlayer dielectric layer 130 is exposed. As a result of the planarization process, the upper capping patterns 120 may be locally formed in the gaps 180 . The lower capping pattern 110 and the upper capping pattern 120 may constitute a capping pattern CAP. The gate structure GS may be composed or formed of the gate electrode GE, the gate dielectric pattern GI, the capping pattern CAP, and the gate spacer GSP.

[0049] Contact holes 140H may be formed in the interlayer dielectric layer 130 on opposite sides of the gate structure GS. The contact holes 140H may expose the source/drain regions SD on opposite sides of the gate structure GS. The formation of the contact holes 140H may include performing an etching process to etch the interlayer dielectric layer 130 under etching conditions having etching selectivity to the capping patterns CAP and the gate spacers GSP. Since the upper capping layer 187 is formed to have a density greater than that of the lower capping layer 182 , the upper capping pattern 120 may exhibit greater resistance to etching than that of the lower capping pattern 110 when an etching process is performed to form the contact hole 140H Etchability.

[0050] Generally, the capping pattern on the gate electrode may be formed as a single pattern including silicon nitride. through the H 2 The capping pattern is formed by a deposition process performed in an atmosphere with a relatively high plasma density. In this case, when the deposition process is performed, hydrogen may diffuse into the gate electrode, and thus, it may be difficult to control the threshold voltage of the gate electrode.

[0051] According to some embodiments, the capping pattern CAP may be formed as a multi-layered structure including the upper capping pattern 120 and the lower capping pattern 110 . through the H 2 The second deposition process is performed in an atmosphere with a relatively high plasma density to form the upper capping pattern 120, and the upper capping pattern 120 can be formed by 2 The first deposition process is performed in an atmosphere with a relatively low plasma density to form the lower capping pattern 110 . In this case, the diffusion of hydrogen into the gate electrode GE may be minimized or reduced during the first deposition process, after which the lower capping pattern 110 may be in the first step for forming the upper capping pattern 120. The diffusion of hydrogen into the gate electrode GE is suppressed or prevented during the second deposition process. Therefore, the threshold voltage of the gate electrode GE can be more easily controlled.

[0052] Also, when an etching process is performed to form the contact holes 140H, the upper capping patterns 120 may exhibit greater etching resistance than that of the lower capping patterns 110 . The upper capping pattern 120 may be formed to cover the topmost surface 110U of the lower capping pattern 110, in which case the lower capping pattern 110 may be minimally exposed during the etching process for forming the contact hole 140H. Therefore, during the etching process for forming the contact hole 140H, it may be possible to minimize or prevent the loss of the capping pattern CAP, and the process margin of the etching process may be maintained.

[0053] Therefore, not only can a process margin be safely obtained in manufacturing a semiconductor device, but the semiconductor device can also have an improvement in electrical characteristics.

[0054] back to reference figure 1 and figure 2 , the contact 140 may be formed in the contact hole 140H. The formation of the contacts 140 may include forming a conductive layer filling the contact holes 140H on the interlayer dielectric layer 130 and planarizing the conductive layer until the interlayer dielectric layer 130 is exposed. Contacts 140 may include, for example, one or more of doped semiconductors, metals, metal silicides, and conductive metal nitrides. Although not shown, wirings (not shown) may be formed on the interlayer dielectric layer 130 to be connected with the contacts 140 . The wirings may be electrically connected to the source/drain regions SD through the contacts 140 .

[0055] Figure 11 shows along figure 1 Cross-sectional views taken along line II', line II-II', and line III-III' of , showing a semiconductor device according to an exemplary embodiment. In order to simplify the description, the following description will focus on and refer to Figure 1 to Figure 3 Differences in the semiconductor devices in question.

[0056] refer to figure 1 and Figure 11 , the capping pattern CAP may include an upper capping pattern 120 and a lower capping pattern 110 . The upper capping pattern 120 may be spaced apart from the gate electrode GE across the lower capping pattern 110 . Also, the upper capping pattern 120 may be spaced apart from each of the gate spacers GSP across the lower capping pattern 110 . For example, the lower capping pattern 110 may be located between the upper capping pattern 120 and the gate electrode GE and between the upper capping pattern 120 and the gate spacer GSP.

[0057] The lower capping pattern 110 may include a first portion 110P1 between the gate electrode GE and the upper capping pattern 120 and a second portion 110P2 extending from the first portion 110P1 to a corresponding side surface of the upper capping pattern 120 . The lower capping pattern 110 may be shaped in a U shape when viewed in cross section. The gate dielectric pattern GI may extend between each of the gate spacers GSP and the gate electrode GE so as to be in contact with the lower capping pattern 110 . For example, the topmost surface of the gate dielectric pattern GI may be in contact with the lower surface of the lower capping pattern 110 . In addition, each of the gate spacers GSP may have a topmost surface in contact with the lower capping patterns 110 . In some embodiments, the topmost surface of the gate spacer GSP may be an inclined surface extending from one side surface of the gate spacer GSP to the other side surface of the gate spacer GSP and facing the capping pattern 110 downward.

[0058] The upper capping pattern 120 may include a body 120BP and a protrusion 120PP protruding from the body 120BP toward the substrate 100 . The body 120BP may have a first width W1, and the protrusion 120PP may have a second width W2 smaller than the first width W1. In some embodiments, the first width W1 may be a first width range, the second width W2 may be a second width range, and the first width range may be larger than the second width range. For example, the body 120BP may have a first width W1 that decreases vertically (eg, the first width is larger at the bottom of the body 120BP and smaller at the top of the body 120BP), and the protrusion 120PP may have a vertical width W1 A second width W2 that increases in direction (eg, the second width is smaller at the bottom of the protrusion 120PP and larger at the top of the protrusion 120PP). In this example, the widest first width W1 of the body 120BP is larger than the widest second width W2 of the protrusion 120PP.

[0059] The protrusions 120PP of the upper capping patterns 120 may be interposed between the second portions 110P2 of the lower capping patterns 110, and a portion of the main body 120BP of the upper capping patterns 120 may cover the topmost surface of each of the second portions 110P2 of the lower capping patterns 110 110U. The topmost surface 110U of the lower capping pattern 110 may be located at a height lower than that of the top surface 120U of the body 120BP of the upper capping pattern 120 with respect to the substrate 100 in the vertical direction. The top surface 130U of the interlayer dielectric layer 130 may be substantially coplanar with the top surface 120U of the upper capping pattern 120 (or with the top surface 120U of the body 120BP of the upper capping pattern 120 ).

[0060] The gate structure GS may include a first region R1 and a second region R2, opposite sides of the first region R1 are provided with the contact 140, and opposite sides of the second region R2 are provided without the contact 140. At the first region R1 of the gate structure GS, the capping pattern CAP may be in contact with the contact 140 . For example, at the first region R1 of the gate structure GS, the lower capping pattern 110 may be in contact with the contact 140 . For example, at the first region R1 of the gate structure GS, each of the second portions 110P2 of the lower capping pattern 110 may be in contact with the contact 140 and may be placed between the contact 140 and the protrusions 120PP of the upper capping pattern 120 between. The second portion 110P2 of the lower capping pattern 110 may separate the protrusions 120PP of the upper capping pattern 120 from the contacts 140 . At the first region R1 of the gate structure GS, the body 120BP of the upper capping pattern 120 may be in contact with the contact 140 . At the second region R2 of the gate structure GS, the capping pattern CAP may be in contact with the interlayer dielectric layer 130 . For example, at the second region R2 of the gate structure GS, each of the second portions 110P2 of the lower capping patterns 110 may be in contact with the interlayer dielectric layer 130 and may be interposed between the interlayer dielectric layer 130 and the upper capping layer Between the protrusions 120PP of the pattern 120 . The second portion 110P2 of the lower capping pattern 110 may separate the protrusions 120PP of the upper capping pattern 120 from the interlayer dielectric layer 130 . At the second region R2 of the gate structure GS, the body 120BP of the upper capping pattern 120 may be in contact with the interlayer dielectric layer 130 .

[0061] Figure 12 and Figure 13 shows along figure 1 Cross-sectional views taken along line II', line II-II', and line III-III' of , illustrating a method of fabricating a semiconductor device according to an exemplary embodiment. E.g, Figure 12 and Figure 13 manufacturing is shown Figure 11 An exemplary method of a semiconductor device. In order to simplify the description, the following description will focus on and refer to Figure 4 to Figure 10 Differences in the manufacturing method discussed.

[0062] as reference Figure 4 to Figure 6As discussed, the substrate 100 may be provided thereon with the device isolation layer ST defining the active pattern ACT and the sacrificial gate pattern 160 extending across the active pattern ACT. Etch stop patterns 150 may be formed under the sacrificial gate patterns 160 , and gate spacers GSP may be formed on corresponding side surfaces of the sacrificial gate patterns 160 . Source/drain regions SD may be formed in the active patterns ACT on opposite sides of the sacrificial gate patterns 160, and an interlayer dielectric layer 130 may be formed to cover the sacrificial gate patterns 160 and the source/drain regions SD. The sacrificial gate pattern 160 and the etch stop pattern 150 may be removed to form a gap 180 between the gate spacers GSP in the interlayer dielectric layer 130 . The gate electrode GE and the gate dielectric pattern GI may be formed to fill the lower portion of the gap 180 .

[0063] refer to Figure 12 , the upper portion of the gate spacer GSP may be removed, and thus, the interlayer dielectric layer 130 may be provided therein with a recessed region 181 exposing the inner surface of the interlayer dielectric layer 130 . The recessed region 181 may be defined by the inner surface of the interlayer dielectric layer 130, the top surface of the gate electrode GE, the topmost surface of the gate dielectric pattern GI, and the topmost surface of the gate spacer GSP. The removal of the upper portion of the gate spacer GSP may include performing an etching process with etching selectivity to the interlayer dielectric layer 130 , the gate electrode GE, and the gate dielectric pattern GI.

[0064] A lower capping layer 182 may be formed on the interlayer dielectric layer 130 to partially fill the recessed region 181 . The lower capping layer 182 may be formed to conformally cover the inner surface of the recessed region 181 . A mask pattern 185 may be formed in the recessed region 181 to partially cover the lower capping layer 182 . The formation of the lower capping layer 182 and the mask pattern 185 can be performed with reference to Figure 7 The manufacturing method discussed is essentially the same.

[0065] refer to Figure 13 , other parts of the lower capping layer 182 not covered by the mask pattern 185 may be removed to form the lower capping pattern 110 . The lower capping pattern 110 may be interposed between the mask pattern 185 and the gate electrode GE and between the mask pattern 185 and the gate dielectric pattern GI, and may extend onto side surfaces of the mask pattern 185 . The topmost surface 110U of the lower capping pattern 110 may be located at substantially the same level as the top surface of the mask pattern 185 with respect to the substrate 100 in the vertical direction.

[0066] Subsequent processes can be compared with reference figure 2 , Figure 9 and Figure 10 The manufacturing method discussed is essentially the same.

[0067] Figure 14 shows along figure 1 Cross-sectional views taken along line II', line II-II', and line III-III' of , showing a semiconductor device according to an exemplary embodiment. In order to simplify the description, the following description will focus on and refer to Figure 1 to Figure 3 Differences in the semiconductor devices in question.

[0068] refer to figure 1 and Figure 14 , the capping pattern CAP may include an upper capping pattern 120 located on the gate electrode GE and a lower capping pattern 110 located between the gate electrode GE and the upper capping pattern 120 . Each of the lower capping patterns 110 and the upper capping patterns 120 may extend in the second direction D2 along the top surface of the gate electrode GE when viewed in a plane. The upper capping pattern 120 may be spaced apart from the gate electrode GE across the lower capping pattern 110 . For example, the lower capping pattern 110 may be located between the upper capping pattern 120 and the gate electrode GE and between the upper capping pattern 120 and the gate dielectric pattern GI.

[0069] Each of the lower capping pattern 110 and the upper capping pattern 120 may have a rectangular shape when viewed in cross section. The gate dielectric pattern GI may extend between each of the gate spacers GSP and the gate electrode GE so as to be in contact with the lower capping pattern 110 . For example, the topmost surface of the gate dielectric pattern GI may be in contact with the bottom surface of the lower capping pattern 110 . The upper capping pattern 120 may cover the topmost surface 110U of the lower capping pattern 110 , and the top surface 130U of the interlayer dielectric layer 130 may be substantially coplanar with the top surface 120U of the upper capping pattern 120 . The topmost surface 110U of the lower capping pattern 110 may be located at a height lower than that of the top surface 130U of the interlayer dielectric layer 130 with respect to the substrate 100 in the vertical direction. The upper capping pattern 120 may be in contact with the topmost surface 110U of the lower capping pattern 110 .

[0070] The gate structure GS may include a first region R1 and a second region R2, opposite sides of the first region R1 are provided with the contacts 140, and opposite sides of the second region R2 are provided without the contacts 140. At the first region R1 of the gate structure GS, the upper capping pattern 120 may be in contact with the contact 140 . At the second region R2 of the gate structure GS, the gate spacers GSP may extend onto corresponding side surfaces of the capping patterns CAP, and the topmost surface of each of the gate spacers GSP may be connected with the interlayer dielectric layer The top surface 130U of 130 is substantially coplanar. Each of the gate spacers GSP may be interposed between the capping patterns CAP and the interlayer dielectric layer 130 and make contact with the lower capping patterns 110 and the upper capping patterns 120 .

[0071] Figure 15 shows along figure 1 Cross-sectional views taken along line II', line II-II', and line III-III' of , illustrating a method of fabricating a semiconductor device according to an exemplary embodiment. E.g, Figure 15 manufacturing is shown Figure 14 An exemplary method of a semiconductor device. In order to simplify the description, the following description will focus on and refer to Figure 4 to Figure 10 Differences in the manufacturing method discussed.

[0072] as reference Figure 4 to Figure 6 As discussed, the substrate 100 may be provided thereon with the device isolation layer ST defining the active pattern ACT and the sacrificial gate pattern 160 across the active pattern ACT. Etch stop patterns 150 may be formed under the sacrificial gate patterns 160 , and gate spacers GSP may be formed on corresponding side surfaces of the sacrificial gate patterns 160 . Source/drain regions SD may be formed in the active patterns ACT on opposite sides of the sacrificial gate patterns 160, and an interlayer dielectric layer 130 may be formed to cover the sacrificial gate patterns 160 and the source/drain regions SD. The sacrificial gate pattern 160 and the etch stop pattern 150 may be removed to form a gap 180 between the gate spacers GSP. The gate electrode GE and the gate dielectric pattern GI may be formed to fill the lower portion of the gap 180 .

[0073] refer to Figure 15 , a lower capping layer (not shown) may be formed on the interlayer dielectric layer 130 to fill the upper portion of the gap 180 . The lower capping layer may be formed to substantially completely fill the upper portion of the gap 180 . The formation of the lower capping layer may include performing a first deposition process. can be in its H 2 The first deposition process is performed in an atmosphere with a relatively low plasma density. For example, the first deposition process may include indirect H 2 Plasma treated or not including H 2 Plasma treatment. The lower capping layer may include, for example, silicon nitride. The lower capping layer may be etched until a desired thickness or depth in the vertical direction is reached in the gap 180 to form the lower capping pattern 110 .

[0074] Subsequent processes can be compared with reference figure 2 , Figure 9 and Figure 10 The manufacturing method discussed is essentially the same.

[0075] Figure 16 shows along figure 1 Cross-sectional views taken along line II', line II-II', and line III-III' of , showing a semiconductor device according to an exemplary embodiment. In order to simplify the description, the following description will focus on and refer to Figure 1 to Figure 3 Differences in the semiconductor devices in question.

[0076] refer to figure 1 and Figure 16 , the capping pattern CAP may include an upper capping pattern 120 on the gate electrode GE and a lower capping pattern 110 between the gate electrode GE and the upper capping pattern 120 . Each of the lower capping patterns 110 and the upper capping patterns 120 may extend in the second direction D2 along the top surface of the gate electrode GE when viewed in a plan view. The upper capping pattern 120 may be spaced apart from the gate electrode GE across the lower capping pattern 110 . Also, the upper capping pattern 120 may be spaced apart from each of the gate spacers GSP across the lower capping pattern 110 . For example, the lower capping pattern 110 may be located between the upper capping pattern 120 and the gate electrode GE and between the upper capping pattern 120 and the gate spacer GSP.

[0077] The gate dielectric pattern GI may extend between each of the gate spacers GSP and the gate electrode GE so as to be in contact with the lower capping pattern 110 . Each of the gate spacers GSP may have a topmost surface in contact with the lower capping patterns 110 . The upper capping pattern 120 may cover the topmost surface 110U of the lower capping pattern 110 , and the top surface 130U of the interlayer dielectric layer 130 may be substantially coplanar with the top surface 120U of the upper capping pattern 120 . The topmost surface 110U of the lower capping pattern 110 may be located at a height lower than that of the top surface 130U of the interlayer dielectric layer 130 with respect to the substrate 100 in the vertical direction. The upper capping pattern 120 may be in contact with the topmost surface 110U of the lower capping pattern 110 . In some embodiments, the topmost surface of the gate spacer GSP may be an inclined surface extending from one side surface of the gate spacer GSP to the other side surface of the gate spacer GSP and facing the capping pattern 110 downward.

[0078] The gate structure GS may include a first region R1 and a second region R2, opposite sides of the first region R1 are provided with the contacts 140, and opposite sides of the second region R2 are provided without the contacts 140. At the first region R1 of the gate structure GS, the lower capping patterns 110 and the upper capping patterns 120 may be in contact with the contacts 140 . At the second region R2 of the gate structure GS, the lower capping patterns 110 and the upper capping patterns 120 may be in contact with the interlayer dielectric layer 130 .

[0079] Figure 17 shows along figure 1 Cross-sectional views taken along line II', line II-II', and line III-III' of , illustrating a method of fabricating a semiconductor device according to an exemplary embodiment. E.g, Figure 17 manufacturing is shown Figure 16 An exemplary method of a semiconductor device. In order to simplify the description, the following description will focus on and refer to Figure 4 to Figure 10 Differences in the manufacturing method discussed.

[0080] as reference Figure 4 to Figure 6 As discussed, the substrate 100 may be provided thereon with the device isolation layer ST defining the active pattern ACT and the sacrificial gate pattern 160 across the active pattern ACT. Etch stop patterns 150 may be formed under the sacrificial gate patterns 160 , and gate spacers GSP may be formed on corresponding side surfaces of the sacrificial gate patterns 160 . Source/drain regions SD may be formed in the active patterns ACT on opposite sides of the sacrificial gate patterns 160, and an interlayer dielectric layer 130 may be formed to cover the sacrificial gate patterns 160 and the source/drain regions SD. The sacrificial gate pattern 160 and the etch stop pattern 150 may be removed to form a gap 180 between the gate spacers GSP. The gate electrode GE and the gate dielectric pattern GI may be formed to fill the lower portion of the gap 180 .

[0081] refer to Figure 17, the upper portion of the gate spacer GSP may be removed, and thus, the interlayer dielectric layer 130 may be provided therein with a recessed region 181 exposing the inner surface of the interlayer dielectric layer 130 . The recessed region 181 may be defined by the inner surface of the interlayer dielectric layer 130, the top surface of the gate electrode GE, the topmost surface of the gate dielectric pattern GI, and the topmost surface of the gate spacer GSP. The removal of the upper portion of the gate spacer GSP may include performing an etching process with etching selectivity to the interlayer dielectric layer 130 , the gate electrode GE, and the gate dielectric pattern GI.

[0082] A lower capping layer (not shown) may be formed on the interlayer dielectric layer 130 to fill the recessed regions 181 . The lower capping layer may be formed to substantially completely fill the recessed region 181 . The formation of the lower capping layer may include performing a first deposition process. available in H 2 The first deposition process is performed in an atmosphere with a relatively low plasma density. For example, the first deposition process may include indirect H 2 Plasma treated or not including H 2 Plasma treatment. The lower capping layer may include, for example, silicon nitride. The lower capping layer may be etched until a desired thickness or depth in the vertical direction is reached in the recessed region 181 to form the lower capping pattern 110 .

[0083] Subsequent processes can be compared with reference figure 2 , Figure 9 and Figure 10 The manufacturing method discussed is essentially the same.

[0084] Figure 18 A plan view illustrating a semiconductor device according to an exemplary embodiment is shown. Figure 19 shows along Figure 18 Cross-sectional views taken on line II' and line II-II'. In order to simplify the description, the following description will focus on and refer to Figure 1 to Figure 3 Differences in the semiconductor devices in question.

[0085] refer to Figure 18 and Figure 19 , the gate structure GS may include a first gate structure GS1 overlapping with the first channel region CH1 and a second gate structure GS2 overlapping with the second channel region CH2. The first channel region CH1 may have a smaller channel length (eg, the length in the direction D1 ) than the channel length (eg, the length in the direction D1 ) of the second channel region CH2 . In some embodiments, each of the first gate structure GS1 and the second gate structure GS2 may include a gate electrode GE, a gate dielectric pattern GI, a gate spacer GSP, and a capping pattern CAP. The capping pattern CAP may include an upper capping pattern 120 and a lower capping pattern 110 . The first gate structure GS1 and the second gate structure GS2 may be configured to be substantially the same as each other except for the gate lengths that are different from each other. For example, in Figure 18 and Figure 19 In the embodiment of the present invention, the width of the first gate structure GS1 in the direction D1 may be smaller than the width of the second gate structure GS2 in the direction D1.

[0086] Figure 20 shows along Figure 18 Cross-sectional views taken along line II' and line II-II' of , which illustrate a semiconductor device according to an exemplary embodiment. In order to simplify the description, the following description will focus on and refer to Figure 1 to Figure 3 Differences in the semiconductor devices in question.

[0087] refer to Figure 18 and Figure 20 , the gate structure GS may include a first gate structure GS1 overlapping with the first channel region CH1 and a second gate structure GS2 overlapping with the second channel region CH2. The first channel region CH1 may have a smaller channel length (eg, the length in the direction D1 ) than the channel length (eg, the length in the direction D1 ) of the second channel region CH2 . In some embodiments, each of the first gate structure GS1 and the second gate structure GS2 may include a gate electrode GE, a gate dielectric pattern GI, and a gate spacer GSP. The first gate structure GS1 may include a capping pattern CAP. The capping pattern CAP may include an upper capping pattern 120 and a lower capping pattern 110 . On the contrary, the second gate structure GS2 may include the single-layer capping pattern CAP_1. The single-layer capping pattern CAP_1 may include the same material as that of the upper capping pattern 120 , and may be formed by performing the same deposition process as that used to form the upper capping pattern 120 . The lower capping pattern 110 may be selectively provided only to the first gate structure GS1. The single-layer capping pattern CAP_1 may be in contact with the gate electrode GE and the gate dielectric pattern GI included in the second gate structure GS2. Each of the gate spacers GSP included in the second gate structure GS2 may be interposed between the single-layer capping pattern CAP_1 and the interlayer dielectric layer 130 .

[0088] According to some exemplary embodiments, the capping pattern CAP may be formed as a multi-layered structure including the upper capping pattern 120 and the lower capping pattern 110 . The lower overlay pattern 110 can be passed through the H 2 formed by performing a first deposition process in an atmosphere with a relatively low plasma density. In this case, the diffusion of hydrogen into the gate electrode GE may be minimized or reduced during the first deposition process, after which the lower capping pattern 110 may be in the first step for forming the upper capping pattern 120. The diffusion of hydrogen into the gate electrode GE is suppressed or prevented during the second deposition process. Therefore, the threshold voltage of the gate electrode GE can be easily controlled.

[0089] Also, when an etching process is performed to form the contact holes 140H, the upper capping patterns 120 may exhibit greater etching resistance than that of the lower capping patterns 110 . The upper capping pattern 120 may be formed to cover the topmost surface 110U of the lower capping pattern 110, and thus, the capping pattern CAP loss may be minimized or prevented during the etching process for forming the contact hole 140H. Therefore, a process margin can be maintained during the etching process for forming the contact holes 140H.

[0090] Therefore, not only a process margin can be safely obtained in manufacturing a semiconductor device, but also the semiconductor device can have an improvement in electrical characteristics.

[0091] The foregoing description provides exemplary embodiments for explaining the inventive concepts. Therefore, the inventive concept is not limited to the above-described embodiments, and it will be understood by those of ordinary skill in the art that changes in form and details may be made therein without departing from the spirit and essential characteristics of the inventive concept.