Instruction verification method and device and storage medium

Abstract

The embodiment of the invention provides an instruction verification method and device and a storage medium, and the method comprises the steps: determining a reserved instruction and a first legal instruction in an instruction file, enabling the value in a first preset bit of the reserved instruction to be null, and enabling the value in a second preset bit of the first legal instruction to be afixed value; generating a first illegal instruction set corresponding to the reserved instruction and a second illegal instruction set corresponding to the first legal instruction, the first illegal instruction set comprising at least one illegal instruction corresponding to the reserved instruction, and the second illegal instruction set comprises at least one illegal instruction corresponding tothe first legal instruction; and executing illegal instructions in the first illegal instruction set and the second illegal instruction set through the processor to determine a consistency result ofthe processor and the instruction file. The method and the device are used for improving instruction consistency verification efficiency.

Description

technical field [0001] The embodiments of the present invention relate to the field of computer technology, and in particular, to an instruction verification method, device and storage medium. Background technique [0002] When developing a processor, a corresponding instruction file is usually configured, and the instruction file includes all instructions that the processor can execute. [0003] In order to ensure the security of the processor, it is necessary to make the processor and the instruction file have instruction consistency. Wherein, the instruction consistency between the processor and the instruction file means that the processor can only execute instructions included in the instruction file, that is, when the processor executes instructions not included in the instruction file, the processor needs to report an error. In the prior art, for a processor with a fixed-length instruction set, it usually executes all possible combinations of instructions, and judges...

AI Technical Summary

Problems solved by technology

[0004] However, in the above process, a large number of instructions need to be verified, resulting in low efficiency of instruction consistency verification

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