FPGA-based multi-source single-output reset method, device and related equipment

Abstract

The invention discloses an FPGA-based multi-source single-output reset method, comprising: acquiring configuration information of a module to be reset; determining each target reset source of the module to be reset and the target reset source of each target reset source according to the configuration information The reset sequence of signals, and the delay period between the various target reset signals under the reset sequence; according to the reset sequence, when the time satisfies the corresponding delay period, the corresponding target reset signal is used for the delay period The module to be reset is reset. In the above-mentioned reset method, each target reset signal related to the module to be reset is reset according to the reset sequence and when the time satisfies the corresponding delay period, the module to be reset is reset according to the corresponding target reset signal, avoiding the target The problem of incomplete reception of the reset signal.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an FPGA-based multi-source single-output reset method, device and related equipment. Background technique [0002] With the increasingly widespread application of heterogeneous acceleration, field-programmable gate array FPGA-based accelerator cards are also developing rapidly. The accelerator card FPGA is connected to the server host through the PCIE interface, and the server host sends the data to be accelerated to the accelerator card FPGA through the PCIE interface, and the accelerator card FPGA returns relevant data through the PCIE interface after processing. In order to support the processing of the application by the accelerator card, an entire support package is implemented inside the FPGA, which is divided into many small modules, and most of the modules need to be reset. [0003] For the same module, when there may be multiple reset sources, if the port of...

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Problems solved by technology

[0004] In view of this, the present invention provides an FPGA-based multi-source single-output reset method, device and related equipment to solve the problem in the prior art that for the same module, when there may be multiple reset sources, if the port of the module If it has been fixed, only one reset input signal can be received, which leads to the incomplete reception of the target reset signal of the module. The specific solution is as follows:

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