FPGA-based multi-source single-output reset method and device and related equipment

Abstract

The invention discloses a FPGA-based multi-source single-output reset method. The method comprises the steps of obtaining configuration information of a to-be-reset module; determining each target reset source of a to-be-reset module, a reset sequence of target reset signals of each target reset source and a delay period among the target reset signals in the reset sequence according to the configuration information; and resetting the to-be-reset module according to the reset sequence and the corresponding target reset signal when the time meets the corresponding delay period. According to thereset method, the target reset signals related to the to-be-reset module are reset according to the reset sequence, when the time meets the corresponding delay period, the to-be-reset module is resetaccording to the corresponding target reset signals, and the problem that the target reset signals are not completely received is avoided.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an FPGA-based multi-source single-output reset method, device and related equipment. Background technique [0002] With the increasingly widespread application of heterogeneous acceleration, field-programmable gate array FPGA-based accelerator cards are also developing rapidly. The accelerator card FPGA is connected to the server host through the PCIE interface, and the server host sends the data to be accelerated to the accelerator card FPGA through the PCIE interface, and the accelerator card FPGA returns relevant data through the PCIE interface after processing. In order to support the processing of the application by the accelerator card, an entire support package is implemented inside the FPGA, which is divided into many small modules, and most of the modules need to be reset. [0003] For the same module, when there may be multiple reset sources, if the port of...

AI Technical Summary

Problems solved by technology

[0004] In view of this, the present invention provides an FPGA-based multi-source single-output reset method, device and related equipment to solve the problem in the prior art that for the same module, when there may be multiple reset sources, if the port of the module If it has been fixed, only one reset input signal can be received, which leads to the incomplete reception of the target reset signal of the module. The specific solution is as follows:

Images