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De-emphasis type continuous-time linear equalizer architecture

A linear equalizer and de-emphasis technology, applied in balanced-unbalanced networks, baseband systems, shaping networks in transmitter/receiver, etc. The same problem, to achieve the effect of increasing the Nyquist frequency, improving the peaking ability, and extending the bandwidth

Pending Publication Date: 2021-07-09
SOUTH UNIVERSITY OF SCIENCE AND TECHNOLOGY OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This patented technology improves upon existing methods for correcting errors caused during transmission over communication networks such as wireless or wireside radio systems. It uses two types of filters with different characteristics that can help reduce interference between signals transmitted simultaneously on both channels. By adding extra circuitry to increase filtering capabilities along certain frequencies, this system becomes more effective when used across multiple bands where there may have been many occurrences of error-correction coding (ECC).

Problems solved by technology

This patents describes how conventional CMOS integrated circuits can be improved over time when they work at very fast speeds. One technical solution involves adding extra components like resistance or inductor elements between certain parts of the chip's structure called nodes. These added structures help reduce impedances and prevent interference effects on the received waveform. By adjusting these parameters based upon the type of impulse noise being generated, this method helps achieve better image performance even if there were any differences in distance traveled along the line path.

Method used

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  • De-emphasis type continuous-time linear equalizer architecture
  • De-emphasis type continuous-time linear equalizer architecture
  • De-emphasis type continuous-time linear equalizer architecture

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0058] refer to Figure 2 to Figure 4 It is a schematic structural diagram of a de-emphasis continuous-time linear equalizer architecture related to Embodiment 1.

[0059] refer to figure 2 , the equalizer main circuit 100 further includes a first input transistor network 12 , a first load impedance network 11 and a first degenerate RC network 13 . Among them, the main input interface V in+ , main input interface V in- , the secondary output interface, the first degenerate RC network 13 and the first load impedance network 11 are respectively connected to the first input transistor network 12, and the first load impedance network 11 and the first input transistor network 12 are connected to the main output interface V out . The first degenerate RC network 13 is also connected to the secondary input interface with the first input transistor network 12 . The end of the first load impedance network 11 away from the first input transistor 12 is connected to a DC voltage sour...

Embodiment 2

[0079] refer to Figure 5 with Figure 7 It is a specific structural diagram of the de-emphasis continuous-time linear equalizer architecture related to the second embodiment.

[0080] refer to Figure 5 , the equalizer main circuit 100 is multi-stage, at least including a first-level main circuit 101 and a second-level main circuit 102 connected with the first-level main circuit 101, and the first-level main circuit 101 includes a first input transistor network 12, a first load impedance network 11 and the first degenerate RC network 13 , the secondary main circuit 102 includes a second input transistor network 22 , a second load impedance network 21 and a second degenerate RC network 23 . Among them, the main input interface V in+ , main input interface V in- respectively connected to the first input transistor network 12, the main output interface V out Connected to the second input transistor network 22 and the second load impedance network 21 , the secondary input in...

Embodiment 3

[0089] refer to Image 6 with Figure 8 It is a specific structural diagram of the de-emphasis continuous-time linear equalizer architecture related to the third embodiment.

[0090] refer to Image 6 , the equalizer main circuit 100 is multi-stage, at least including a first-level main circuit 101 and a second-level main circuit 102 connected with the first-level main circuit 101, and the first-level main circuit 101 includes a first input transistor network 12, a first load impedance network 11 and the first degenerate RC network 13 , the secondary main circuit 102 includes a second input transistor network 22 , a second load impedance network 21 and a second degenerate RC network 23 . Among them, the main input interface V in+ and main input interface V in- Connected to the second input transistor network 22, the main output interface V out Connected to the first input transistor network 12 and the first load impedance network 11 , the secondary input interface and the...

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Abstract

The embodiment of the invention discloses a de-emphasis type continuous-time linear equalizer architecture, and the architecture comprises an equalizer main circuit, a de-emphasis type continuous-time linear equalizer main circuit, a de-emphasis type continuous-time linear equalizer main circuit and a de-emphasis type continuous-time linear equalizer main circuit, wherein the equalizer main circuit is used for performing first equalization processing on a first differential signal input from the main input interface so as to output a second differential signal to the auxiliary output interface; a de-emphasis circuit which is connected with an auxiliary input interface and an auxiliary output interface of the equalizer main circuit, comprises a filter and an amplifier connected with the filter, and is used for performing second equalization processing on a second differential signal input by the auxiliary output interface so as to output a third differential signal to the auxiliary input interface; wherein the equalizer main circuit outputs a fourth differential signal from the main output interface based on the first differential signal and the third differential signal. The de-emphasis type continuous-time linear equalizer architecture disclosed by the invention can improve peaking capability and make up channel loss, and has the characteristic of low cost.

Description

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Claims

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Application Information

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Owner SOUTH UNIVERSITY OF SCIENCE AND TECHNOLOGY OF CHINA
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