Chip clock tree planning method and chip

A clock tree synthesis and chip technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve the problems of clock convergence frequency influence, clock convergence difficulty, etc., to reduce the difficulty of clock convergence and increase the frequency of clock convergence Effect

Pending Publication Date: 2021-07-30
XI AN UNIIC SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] Due to the increasing area of ​​the chip, in the existing clock design scheme, OCV (On Chip Variation, on-chip variable) will affect the frequency of clock convergence when performing synchronous design on the chip, making clock convergence difficult

Method used

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  • Chip clock tree planning method and chip
  • Chip clock tree planning method and chip
  • Chip clock tree planning method and chip

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Embodiment Construction

[0021] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

[0022] The terms "first", "second", and "third" in this application are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, features defined as "first", "second", and "third" may explicitly or implicitly include at least one of these features. In the description of the present application, "plurality" means at least t...

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PUM

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Abstract

The invention provides a clock tree planning method of a chip and the chip. The method comprises the following steps: planning the area range of each clock domain based on an on-chip variable corresponding to a current process and the area of the chip; wiring in the area range corresponding to each clock domain according to a preset rule so as to obtain clock tree synthesis of each clock domain; and synthesizing and splicing the clock trees of all the clock domains. Therefore, the clock convergence frequency is improved, and the clock convergence difficulty is reduced.

Description

technical field [0001] The invention relates to the field of clocks, in particular to a chip clock tree planning method and the chip. Background technique [0002] As the area of ​​the chip is getting bigger and bigger, in the existing clock design scheme, when performing synchronous design on the chip, OCV (On Chip Variation, on-chip variable) will affect the clock convergence frequency, making the clock convergence difficult. Contents of the invention [0003] The invention provides a chip clock tree planning method and a chip, which can increase the frequency of clock convergence and reduce the difficulty of clock convergence. [0004] In order to solve the above technical problems, the first technical solution provided by the present invention is to provide a clock tree planning method for a chip, the method including: planning each clock domain based on the on-chip variables corresponding to the current process and the area of ​​the chip area range; perform wiring in...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/396G06F30/392G06F30/394
CPCG06F30/392G06F30/394G06F30/396
Inventor 韩洋
Owner XI AN UNIIC SEMICON CO LTD
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