Chip clock tree planning method and chip

Abstract

The invention provides a clock tree planning method of a chip and the chip. The method comprises the following steps: planning the area range of each clock domain based on an on-chip variable corresponding to a current process and the area of the chip; wiring in the area range corresponding to each clock domain according to a preset rule so as to obtain clock tree synthesis of each clock domain; and synthesizing and splicing the clock trees of all the clock domains. Therefore, the clock convergence frequency is improved, and the clock convergence difficulty is reduced.

Description

technical field [0001] The invention relates to the field of clocks, in particular to a chip clock tree planning method and the chip. Background technique [0002] As the area of ​​the chip is getting bigger and bigger, in the existing clock design scheme, when performing synchronous design on the chip, OCV (On Chip Variation, on-chip variable) will affect the clock convergence frequency, making the clock convergence difficult. Contents of the invention [0003] The invention provides a chip clock tree planning method and a chip, which can increase the frequency of clock convergence and reduce the difficulty of clock convergence. [0004] In order to solve the above technical problems, the first technical solution provided by the present invention is to provide a clock tree planning method for a chip, the method including: planning each clock domain based on the on-chip variables corresponding to the current process and the area of ​​the chip area range; perform wiring in...

AI Technical Summary

Problems solved by technology

[0002] Due to the increasing area of ​​the chip, in the existing clock design scheme, OCV (On Chip Variation, on-chip variable) will affect the frequency of clock convergence when performing synchronous design on the chip, making clock convergence difficult

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