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Display panel with display area integrated with gate drive circuit

A technology that integrates gate drive and gate drive, which is applied to static indicators, identification devices, instruments, etc., and can solve problems such as data line interference

Active Publication Date: 2021-08-13
WUHAN CHINA STAR OPTOELECTRONICS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In order to solve the problem that when the gate driving signal line and the data line are arranged side by side between the same two adjacent columns of sub-pixels, the data line is easily interfered by the gate driving signal line parallel to it, the embodiment of the present application provides a display area A display panel with an integrated gate drive circuit, the display panel includes sub-pixels arranged in the display area, and gate lines, data lines and gate drive signal lines for driving the sub-pixels, the data lines and the The gate driving signal lines are arranged perpendicular to the gate lines; wherein, the gate driving signal lines are connected to the gate lines, and it is characterized in that the gate driving signal lines are arranged on the same side as the gate driving signal lines. between two columns of subpixels adjacent to the line, the data line is arranged between the two columns of subpixels adjacent to the data line, and only the One of the gate drive signal line and the data line, so that the gate drive signal line and the data line are not arranged side by side between any same two adjacent columns of the sub-pixels

Method used

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  • Display panel with display area integrated with gate drive circuit
  • Display panel with display area integrated with gate drive circuit
  • Display panel with display area integrated with gate drive circuit

Examples

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Embodiment 1

[0049] If the display panel provided in the embodiment of the present application is a 1-to-2 multiplexing display panel, image 3 It is a position distribution diagram of sub-pixels, data lines and gate drive signal lines of the 1-to-2 multiplexing display panel of the embodiment of the present application, Image 6 The circuit connection diagram of the data lines of the 1-to-2 multiplexing display panel provided by the embodiment of the present application is represented by Image 6 Can be seen correspondingly image 3 The actual demux circuit connections for the data lines in .

[0050] Such as image 3 As shown, the 1-to-2 multiplexing display panel includes a plurality of sequentially arranged first repeating units 101, and each first repeating unit 101 includes two groups of periodically arranged red, green and blue sub-pixels, and each sub-pixel corresponds to Data lines, and at least two gate driving signal lines corresponding to each group of red, green and blue sub-...

Embodiment 2

[0060] If the display panel provided in the embodiment of the present application is a 1-to-3 multiplexing display panel, Figure 7 The location distribution diagram of the sub-pixels, data lines and gate drive signal lines of the 1-to-3 multiplexing display panel provided by the embodiment of the present application, Figure 8 It is a circuit connection diagram of the data lines of the 1-to-3 multiplexing display panel of the embodiment of the present application, which is composed of Figure 8 Can be seen correspondingly Figure 7 The actual demux circuit connections for the data lines in .

[0061] Such as Figure 7 As shown, the 1-to-3 multiplexing display panel includes a plurality of second repeating units 102 arranged in sequence, and each second repeating unit 102 includes two groups of red, green and blue sub-pixels arranged periodically, and each sub-pixel corresponds to Data lines, and at least two gate driving signal lines corresponding to each group of red, gre...

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Abstract

The invention provides a display panel with a display area integrated with a gate drive circuit. The display panel is characterized in that a single data line, or a single gate drive signal line, or data lines and data lines arranged side by side, or gate drive signal lines and gate drive signal lines arranged side by side are arranged between any two same adjacent columns of sub-pixels, so that the gate drive signal lines and the data lines are not arranged side by side between any two same adjacent columns of sub-pixels, and the problem that, in order to further reduce the frame of the display panel, the gate drive circuit is led out from the display area, so that data lines and the gate drive signal lines may be arranged side by side between any two same adjacent columns of sub-pixels, the data lines are easily interfered by parasitic capacitance generated between the data lines and the gate drive signal lines, the data voltage maintained when the pixel corresponding to the new data line performs image display is unstable, and the problem that the display panel has abnormal pictures is solved.

Description

technical field [0001] The present application relates to the field of display technology, in particular to a display panel with integrated gate drive circuits in the display area. Background technique [0002] Current gate drive circuits, such as GOA (Gate Driven on Array) circuits are mainly designed on one or both sides of the display panel. With the continuous development of full-screen mobile phones, and in the face of When the application shapes of display panels such as vehicles are more diverse and complex, the frame of the display panel is required to be narrower and narrower. When the width of the gate drive circuit cannot be compressed, the frame of the display panel cannot be reduced any more. Based on this defect, researchers have proposed GIA (Gate Driven in Array) technology, that is, the technology of integrating the gate drive circuit in the display area of ​​the display panel. It is directly drawn from the display area of ​​the display panel, so that the f...

Claims

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Application Information

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IPC IPC(8): G09F9/30G09G3/20
CPCG09F9/30G09G3/20G09G2300/0426G09G2310/0297G09G2300/0452G09G3/3266G09G2300/0408G09G2310/0267
Inventor 田超
Owner WUHAN CHINA STAR OPTOELECTRONICS TECH CO LTD
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